/***********************************************************************
*
* Function: c_entry
*
* Purpose: Application entry point from the startup code
*
* Processing:
* See function.
*
* Parameters: None
*
* Outputs: None
*
* Returns: Nothing
*
* Notes: None
*
**********************************************************************/
void c_entry(void) {
UNS_8 *p8;
INT_32 toread, idx;
PFV execa = (PFV) STAGE1_LOAD_ADDR;
/* Force SSP configuration, use GPIO_05 (SSP0_CS) in software
control mode */
GPIO->p2_dir_set = P2_DIR_GPIO(5);
GPIO->p2_mux_clr = P2_GPIO05_SSEL0;
GPIO->p_mux_set = P_SPI1CLK_SCK0 | P_SPI1DATAIN_SSP0_MISO |
P_SPI1DATAIO_SSP0_MOSI;
board_spi_config();
/* Read data into memory */
toread = STAGE1_LOAD_SIZE;
p8 = (UNS_8 *) STAGE1_LOAD_ADDR;
idx = SPI_S1APP_OFFSET;
while (toread > 0)
{
*p8 = board_spi_read(idx);
p8++;
idx++;
toread--;
}
#ifdef USE_MMU
dcache_flush();
dcache_inval();
icache_inval();
#endif
execa();
}
/***********************************************************************
*
* Function: c_entry
*
* Purpose: Application entry point from the startup code
*
* Processing:
* See function.
*
* Parameters: None
*
* Outputs: None
*
* Returns: Always returns 1, or <0 on an error
*
* Notes: None
*
**********************************************************************/
void c_entry(void)
{
UNS_32 idx;
uart_output_init();
/* Force SSP configuration, use GPIO_05 (SSP0_CS) in software
control mode */
GPIO->p2_dir_set = P2_DIR_GPIO(5);
GPIO->p2_mux_clr = P2_GPIO05_SSEL0;
GPIO->p_mux_set = P_SPI1CLK_SCK0 | P_SPI1DATAIN_SSP0_MISO |
P_SPI1DATAIO_SSP0_MOSI;
board_spi_config();
/* Disable write protect */
spi_flash_wp_disable();
/* Fill first locations with 0's */
for (idx = 0; idx < 8; idx++)
{
board_spi_write(0, idx);
}
uart_output((UNS_8 *)"SPI erased\r\n");
/* Loop forever */
while (1);
}
/**********************************************
ИНИЦИАЛИЗАЦИЯ СИСТЕМЫ ПРЕРЫВАНИЙ
**********************************************/
void InitializeInterruptSystem()
{
/* Initialize interrupt system */
int_initialize(0xFFFFFFFF);
/* Install standard IRQ dispatcher at ARM IRQ vector */
int_install_arm_vec_handler(IRQ_VEC, (PFV) lpc32xx_irq_handler);
/* Install standard FIQ dispatcher at ARM IRQ vector */
int_install_arm_vec_handler(FIQ_VEC, (PFV) lpc32xx_fiq_handler);
//---------------------HSTIMER------------------------------------
/* Install HSTIMER interrupt handler as a IRQ interrupts */
int_install_irq_handler(IRQ_HSTIMER,
(PFV) hstimer_user_interrupt);
// Save address of register block
hst_regptr = HSTIMER;
gpio_regptr = GPIO;
// LEDs off
//gpio_regptr->p3_outp_clr = LED1 | LED2;
//gpio_regptr->p1_dir_set = LED3;
// Enable timer system clock
clkpwr_clk_en_dis(CLKPWR_HSTIMER_CLK, 1);
// Disable high speed timer and match timers
hst_regptr->hstim_ctrl = HSTIM_CTRL_RESET_COUNT;
hst_regptr->hstim_mctrl = 0;
hst_regptr->hstim_ctrl = 0;
// Clear pending interrupts
hst_regptr->hstim_int = (HSTIM_MATCH0_INT |
HSTIM_MATCH1_INT | HSTIM_MATCH2_INT |
HSTIM_GPI_06_INT | HSTIM_RTC_TICK_INT);
hst_regptr->hstim_mctrl = HSTIM_CNTR_MCR_MTCH(0) | HSTIM_CNTR_MCR_RESET(0);
hst_regptr->hstim_pmatch = 13-1;
hst_regptr->hstim_match[0] = 1000;//1ms 000;
hst_regptr->hstim_ctrl = HSTIM_CTRL_COUNT_ENAB;//start hstimer
// Enable interrupt in the interrupt controller
int_enable(IRQ_HSTIMER);
//---------------------SSP1------------------------------------
ssp1_regptr = SSP1; // Pointer to SSP1 registers
// Enable ssp1 system clock
clkpwr_clk_en_dis(CLKPWR_SSP1_CLK, 1);
//конфигурация IO
gpio_regptr->p2_mux_clr = P2_GPIO04_SSEL1;
gpio_regptr->p2_dir_set = P2_DIR_GPIO(4);
gpio_regptr->p3_outp_set = P3_STATE_GPIO(4);
/* The MISO, MOSI, and SCK signals are controlled by the SSP1 */
gpio_regptr->p_mux_set = (P_SPI2DATAIO_MOSI1 |
P_SPI2DATAIN_MISO1 | P_SPI2CLK_SCK1);
ssp1_regptr->cpsr = SSP_CPSR_CPDVSR(16);//8);//4);//4);//prescale
//ssp_clk / ((cr0_div + 1) * prescale);
//prescale = 16; SCR = 4 - 1.25MGz
ssp1_regptr->cr0 = SSP_CR0_DSS(8) |//data size 8 bit
SSP_CR0_FRF_SPI |//Motorola SPI mode
SSP_CR0_SCR(4);//serial clock rate
// Default Master mode
// Disable SSP1
ssp1_regptr->cr1 &= ~SSP_CR1_SSP_ENABLE;
// interr handler SSP1 IRQ
//int_install_irq_handler(IRQ_SSP1, (PFV) ssp1_user_interrupt);
// Enable interrupt in the interrupt controller
//int_enable(IRQ_SSP1);
// Clear interrupt in the interrupt controller
//int_clear(IRQ_SSP1);
// Enable SSP1
ssp1_regptr->cr1 |= SSP_CR1_SSP_ENABLE;
}//InitializeInterruptSystem()