/*
* Get physical memory size
*/
unsigned int
pc98_getmemsize(unsigned int *base, unsigned int *ext)
{
unsigned int under16, over16;
/* available conventional memory size */
*base = ((PC98_SYSTEM_PARAMETER(0x501) & 7) + 1) * 128;
/* available protected memory size under 16MB */
under16 = PC98_SYSTEM_PARAMETER(0x401) * 128 + 1024;
#ifdef EPSON_MEMWIN
if (pc98_machine_type & M_EPSON_PC98) {
if (under16 > (15 * 1024))
/* chop under16 memory to 15MB */
under16 = 15 * 1024;
init_epson_memwin();
}
#endif
/* available protected memory size over 16MB / 1MB */
over16 = PC98_SYSTEM_PARAMETER(0x594);
over16 += PC98_SYSTEM_PARAMETER(0x595) * 256;
if (over16 > 0)
*ext = (16 + over16) * 1024 - 1024;
else
*ext = under16 - 1024;
return (under16);
}
/* probe video adapters and return the number of detected adapters */
static int
probe_adapters(void)
{
video_info_t info;
/* do this test only once */
if (gdc_init_done)
return 1;
gdc_init_done = TRUE;
biosadapter[0] = adapter_init_value[0];
biosadapter[0].va_flags |= V_ADP_PROBED;
biosadapter[0].va_mode =
biosadapter[0].va_initial_mode = biosadapter[0].va_initial_bios_mode;
if ((PC98_SYSTEM_PARAMETER(0x597) & 0x80) ||
(PC98_SYSTEM_PARAMETER(0x458) & 0x80)) {
gdc_FH = (inb(0x9a8) & 1) ? _31KHZ : _24KHZ;
} else {
gdc_FH = _24KHZ;
}
gdc_get_info(&biosadapter[0], biosadapter[0].va_initial_mode, &info);
initialize_gdc(T25_G400, info.vi_flags & V_INFO_GRAPHICS);
biosadapter[0].va_window = BIOS_PADDRTOVADDR(info.vi_window);
biosadapter[0].va_window_size = info.vi_window_size;
biosadapter[0].va_window_gran = info.vi_window_gran;
biosadapter[0].va_buffer = 0;
biosadapter[0].va_buffer_size = 0;
if (info.vi_flags & V_INFO_GRAPHICS) {
switch (info.vi_depth/info.vi_planes) {
case 1:
biosadapter[0].va_line_width = info.vi_width/8;
break;
case 2:
biosadapter[0].va_line_width = info.vi_width/4;
break;
case 4:
biosadapter[0].va_line_width = info.vi_width/2;
break;
case 8:
default: /* shouldn't happen */
biosadapter[0].va_line_width = info.vi_width;
break;
}
} else {
biosadapter[0].va_line_width = info.vi_width;
}
bcopy(&info, &biosadapter[0].va_info, sizeof(info));
verify_adapter(&biosadapter[0]);
return 1;
}
/*
* Get physical memory size
*/
void
pc98_getmemsize(void)
{
unsigned char under16, over16;
/* available protected memory size under 16MB / 128KB */
under16 = PC98_SYSTEM_PARAMETER(0x401);
/* available protected memory size over 16MB / 1MB */
over16 = PC98_SYSTEM_PARAMETER(0x594);
/* add conventional memory size (1024KB / 128KB = 8) */
under16 += 8;
Maxmem = Maxmem_under16M = under16 * 128 * 1024 / PAGE_SIZE;
Maxmem += (over16 * 1024 * 1024 / PAGE_SIZE);
#ifdef EPSON_MEMWIN
init_epson_memwin();
#endif
}
/*
* Read a geometry information of SCSI HDD from BIOS work area.
*
* XXX - Before reading BIOS work area, we should check whether
* host adapter support it.
*/
int
scsi_da_bios_params(struct ccb_calc_geometry *ccg)
{
#if NDA > 0
u_char *tmp;
int target;
int bus;
target = ccg->ccb_h.target_id;
bus = 0; /* If your really need to know, send a PathInq CCB */
tmp = (u_char *)&PC98_SYSTEM_PARAMETER(0x460 + target*4);
if ((PC98_SYSTEM_PARAMETER(0x482) & ((1 << target)&0xff)) != 0) {
ccg->secs_per_track = *tmp;
ccg->cylinders = ((*(tmp+3)<<8)|*(tmp+2))&0xfff;
#if 0
switch (*(tmp + 3) & 0x30) {
case 0x00:
disk_parms->secsiz = 256;
printf("Warning!: not supported.\n");
break;
case 0x10:
disk_parms->secsiz = 512;
break;
case 0x20:
disk_parms->secsiz = 1024;
break;
default:
disk_parms->secsiz = 512;
printf("Warning!: not supported. But force to 512\n");
break;
}
#endif
if (*(tmp+3) & 0x40) {
ccg->cylinders += (*(tmp+1)&0xf0)<<8;
ccg->heads = *(tmp+1)&0x0f;
} else {
ccg->heads = *(tmp+1);
}
return 1;
}
#endif /* NDA > 0 */
return 0;
}
static int
verify_adapter(video_adapter_t *adp)
{
#ifndef GDC_NOGRAPHICS
int i;
if (PC98_SYSTEM_PARAMETER(0x45c) & 0x40) { /* PEGC exists */
adp->va_flags |= V_ADP_VESA; /* XXX */
} else {
for (i = 0; bios_vmode[i].vi_mode != EOT; ++i) {
if (bios_vmode[i].vi_flags & V_INFO_VESA)
bios_vmode[i].vi_mode = NA;
}
}
#endif
return 0;
}
static void initialize_gdc(unsigned int mode, int isGraph)
{
#ifdef LINE30
/* start 30line initialize */
int m_mode, s_mode, gdc_clock, hsync_clock;
gdc_clock = check_gdc_clock();
m_mode = (mode == T25_G400) ? _25L : _30L;
s_mode = 2*mode+gdc_clock;
gdc_INFO = m_mode;
master_gdc_wait_vsync();
if ((PC98_SYSTEM_PARAMETER(0x597) & 0x80) ||
(PC98_SYSTEM_PARAMETER(0x458) & 0x80)) {
if (PC98_SYSTEM_PARAMETER(0x481) & 0x08) {
hsync_clock = (m_mode == _25L) ? gdc_FH : _31KHZ;
outb(0x9a8, (hsync_clock == _31KHZ) ? 1 : 0);
} else {
hsync_clock = gdc_FH;
}
} else {
hsync_clock = _24KHZ;
}
if ((gdc_clock == _2_5MHZ) &&
(slave_param[hsync_clock][s_mode][GDC_LF] > 400)) {
outb(0x6a, 0x83);
outb(0x6a, 0x85);
gdc_clock = _5MHZ;
s_mode = 2*mode+gdc_clock;
}
master_gdc_cmd(_GDC_RESET);
master_gdc_cmd(_GDC_MASTER);
gdc_cmd(_GDC_RESET);
gdc_cmd(_GDC_SLAVE);
/* GDC Master */
master_gdc_cmd(_GDC_SYNC);
master_gdc_prm(0x00); /* flush less */ /* text & graph */
master_gdc_prm(master_param[hsync_clock][m_mode][GDC_CR]);
master_gdc_word_prm(((master_param[hsync_clock][m_mode][GDC_HFP] << 10)
+ (master_param[hsync_clock][m_mode][GDC_VS] << 5)
+ master_param[hsync_clock][m_mode][GDC_HS]));
master_gdc_prm(master_param[hsync_clock][m_mode][GDC_HBP]);
master_gdc_prm(master_param[hsync_clock][m_mode][GDC_VFP]);
master_gdc_word_prm(((master_param[hsync_clock][m_mode][GDC_VBP] << 10)
+ (master_param[hsync_clock][m_mode][GDC_LF])));
master_gdc_fifo_empty();
master_gdc_cmd(_GDC_PITCH);
master_gdc_prm(MasterPCH);
master_gdc_fifo_empty();
/* GDC slave */
gdc_cmd(_GDC_SYNC);
gdc_prm(0x06);
gdc_prm(slave_param[hsync_clock][s_mode][GDC_CR]);
gdc_word_prm((slave_param[hsync_clock][s_mode][GDC_HFP] << 10)
+ (slave_param[hsync_clock][s_mode][GDC_VS] << 5)
+ (slave_param[hsync_clock][s_mode][GDC_HS]));
gdc_prm(slave_param[hsync_clock][s_mode][GDC_HBP]);
gdc_prm(slave_param[hsync_clock][s_mode][GDC_VFP]);
gdc_word_prm((slave_param[hsync_clock][s_mode][GDC_VBP] << 10)
+ (slave_param[hsync_clock][s_mode][GDC_LF]));
gdc_fifo_empty();
gdc_cmd(_GDC_PITCH);
gdc_prm(SlavePCH[gdc_clock]);
gdc_fifo_empty();
/* set Master GDC scroll param */
master_gdc_wait_vsync();
master_gdc_wait_vsync();
master_gdc_wait_vsync();
master_gdc_cmd(_GDC_SCROLL);
master_gdc_word_prm(0);
master_gdc_word_prm((master_param[hsync_clock][m_mode][GDC_LF] << 4)
| 0x0000);
master_gdc_fifo_empty();
/* set Slave GDC scroll param */
gdc_wait_vsync();
gdc_cmd(_GDC_SCROLL);
gdc_word_prm(0);
if (gdc_clock == _5MHZ) {
gdc_word_prm((SlaveScrlLF[mode] << 4) | 0x4000);
} else {
gdc_word_prm(SlaveScrlLF[mode] << 4);
}
gdc_fifo_empty();
gdc_word_prm(0);
if (gdc_clock == _5MHZ) {
gdc_word_prm((SlaveScrlLF[mode] << 4) | 0x4000);
} else {
gdc_word_prm(SlaveScrlLF[mode] << 4);
}
gdc_fifo_empty();
/* sync start */
gdc_cmd(isGraph ? _GDC_START : _GDC_STOP);
gdc_wait_vsync();
gdc_wait_vsync();
gdc_wait_vsync();
master_gdc_cmd(isGraph ? _GDC_STOP : _GDC_START);
#else
master_gdc_wait_vsync();
master_gdc_cmd(isGraph ? _GDC_STOP : _GDC_START); /* text */
gdc_wait_vsync();
gdc_cmd(isGraph ? _GDC_START : _GDC_STOP); /* graphics */
#endif
}
