pcireg_t
ht_conf_read(void *cpv, pcitag_t tag, int offset)
{
struct ht_softc *sc = cpv;
int bus, dev, fcn;
pcireg_t reg;
uint32_t val;
val = PCITAG_OFFSET(tag);
#ifdef DEBUG
printf("ht_conf_read: tag=%x, offset=%x\n", val, offset);
#endif
pci_decompose_tag(NULL, tag, &bus, &dev, &fcn);
if (bus == 0 && dev == 0) {
val |= (offset << 2);
reg = bus_space_read_4(sc->sc_iot, sc->sc_config0_ioh, val);
reg = letoh32(reg);
} else if (bus == 0) {
/* XXX Why can we only access function 0? */
if (fcn > 0)
return ~0;
val |= offset;
reg = bus_space_read_4(sc->sc_memt, sc->sc_config0_memh, val);
} else {
val |= offset;
reg = bus_space_read_4(sc->sc_memt, sc->sc_config1_memh, val);
}
#ifdef DEBUG
printf("ht_conf_read: reg=%x\n", reg);
#endif
return reg;
}
void
ht_conf_write(void *cpv, pcitag_t tag, int offset, pcireg_t data)
{
struct ht_softc *sc = cpv;
int bus, dev, fcn;
uint32_t val;
val = PCITAG_OFFSET(tag);
#ifdef DEBUG
printf("ht_conf_write: tag=%x, offset=%x, data = %x\n",
val, offset, data);
#endif
pci_decompose_tag(NULL, tag, &bus, &dev, &fcn);
if (bus == 0 && dev == 0) {
val |= (offset << 2);
data = htole32(data);
bus_space_write_4(sc->sc_iot, sc->sc_config0_ioh, val, data);
bus_space_read_4(sc->sc_iot, sc->sc_config0_ioh, val);
} else if (bus == 0) {
/* XXX Why can we only access function 0? */
if (fcn > 0)
return;
val |= offset;
bus_space_write_4(sc->sc_memt, sc->sc_config0_memh, val, data);
bus_space_read_4(sc->sc_memt, sc->sc_config0_memh, val);
} else {
val |= offset;
bus_space_write_4(sc->sc_memt, sc->sc_config1_memh, val, data);
bus_space_read_4(sc->sc_memt, sc->sc_config1_memh, val);
}
}
u_int32_t
mpc_gen_config_reg(void *cpv, pcitag_t tag, int offset)
{
struct pcibr_config *cp = cpv;
unsigned int bus, dev, fcn;
u_int32_t reg, val = PCITAG_OFFSET(tag);
pci_decompose_tag(cpv, tag, &bus, &dev, &fcn);
if (cp->config_type & 4) {
reg = val | offset | 1;
reg |= (offset >> 8) << 28;
} else if (cp->config_type & 1) {
