static int
ahci_pci_match(device_t parent, cfdata_t match, void *aux)
{
struct pci_attach_args *pa = aux;
bus_space_tag_t regt;
bus_space_handle_t regh;
bus_size_t size;
int ret = 0;
bool force;
force = ((ahci_pci_has_quirk( PCI_VENDOR(pa->pa_id),
PCI_PRODUCT(pa->pa_id)) & AHCI_PCI_QUIRK_FORCE) != 0);
/* if wrong class and not forced by quirks, don't match */
if ((PCI_CLASS(pa->pa_class) != PCI_CLASS_MASS_STORAGE ||
((PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_SATA ||
PCI_INTERFACE(pa->pa_class) != PCI_INTERFACE_SATA_AHCI) &&
PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_RAID)) &&
(force == false))
return 0;
if (pci_mapreg_map(pa, AHCI_PCI_ABAR,
PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
®t, ®h, NULL, &size) != 0)
return 0;
if ((PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_SATA &&
PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_SATA_AHCI) ||
(bus_space_read_4(regt, regh, AHCI_GHC) & AHCI_GHC_AE) ||
(force == true))
ret = 3;
bus_space_unmap(regt, regh, size);
return ret;
}
static int
ppbmatch(device_t parent, cfdata_t match, void *aux)
{
struct pci_attach_args *pa = aux;
/*
* Check the ID register to see that it's a PCI bridge.
* If it is, we assume that we can deal with it; it _should_
* work in a standardized way...
*/
if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_PCI)
return 1;
#ifdef __powerpc__
if (PCI_CLASS(pa->pa_class) == PCI_CLASS_PROCESSOR &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_PROCESSOR_POWERPC) {
pcireg_t bhlc = pci_conf_read(pa->pa_pc, pa->pa_tag,
PCI_BHLC_REG);
if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_FREESCALE
&& PCI_HDRTYPE(bhlc) == PCI_HDRTYPE_RC)
return 1;
}
#endif
#ifdef _MIPS_PADDR_T_64BIT
/* The LDT HB acts just like a PPB. */
if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIBYTE
&& PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIBYTE_BCM1250_LDTHB)
return 1;
#endif
return 0;
}
static void
pci_bridge_hook(pci_chipset_tag_t pc, pcitag_t tag, void *ctx)
{
struct pci_bridge_hook_arg *bridge_hook = (void *)ctx;
pcireg_t reg;
reg = pci_conf_read(pc, tag, PCI_CLASS_REG);
if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE &&
(PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI ||
PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) {
(*bridge_hook->func)(pc, tag, bridge_hook->arg);
}
}
/*
* Compare PCI device parameters (vendor id, device id, subsystem id, etc)
* with those specified in the struct pci_dev_t. vid and did of the struct
* must be defined.
*
* Return TRUE on match, FALSE if else.
*/
int
pci_device_match(struct pci_entry_t *e, struct pci_dev_t *c) {
u_int32_t data;
/* These must be defined */
data = pci_read_reg(e, PCI_ID_REG);
#ifdef DEBUG
if (data != 0xFFFFFFFF) {
printf("bus %u, dev %u, fun %u:", e->bus, e->dev, e->fun);
printf("\tvendor id 0x%x, product id 0x%x\n", PCI_VENDOR(data), PCI_PRODUCT(data));
}
#endif /* DEBUG */
if (PCI_PRODUCT(data) != c->did)
return 0;
if (PCI_VENDOR(data) != c->vid)
return 0;
#ifdef DEBUG
printf("bus %u, dev %u, fun %u:", e->bus, e->dev, e->fun);
printf("\tvendor id 0x%x, product id 0x%x\n", PCI_VENDOR(data), PCI_PRODUCT(data));
data = pci_read_reg(e, PCI_CLASS_REG);
printf("\tclass multimedia, subclass 0x%x, revision 0x%x\n",
PCI_SUBCLASS(data), PCI_REVISION(data));
data = pci_read_reg(e, PCI_SUBSYSVEND_REG);
printf("\tsubsystem vendor id 0x%x, subsystem id 0x%x\n", PCI_VENDOR(data), PCI_PRODUCT(data));
#endif /* DEBUG */
data = pci_read_reg(e, PCI_CLASS_REG);
if (PCI_CLASS(data) != PCI_CLASS_MULTIMEDIA)
return 0;
if (c->subclass != PCI_SUBCLASS_ANY)
if (c->subclass != PCI_SUBCLASS(data))
return 0;
if (c->rev != PCI_REVISION_ANY)
if (c->rev != PCI_REVISION(data))
return 0;
data = pci_read_reg(e, PCI_SUBSYSVEND_REG);
if (c->subvid != PCI_SUBSYS_ID_ANY)
if (c->subvid != PCI_VENDOR(data))
return 0;
if (c->subdid != PCI_SUBSYS_ID_ANY)
if (c->subdid != PCI_PRODUCT(data))
return 0;
return 1;
}
int
sdhc_pci_match(struct device *parent, void *match, void *aux)
{
struct pci_attach_args *pa = aux;
/*
* The Realtek RTS5209 is supported by rtsx(4). Usually the device
* class for these is UNDEFINED but there are RTS5209 devices which
* are advertising an SYSTEM/SDHC device class in addition to a
* separate device advertising the UNDEFINED class. Such devices are
* not compatible with sdhc(4), so ignore them.
*/
if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_REALTEK &&
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_REALTEK_RTS5209)
return 0;
if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SYSTEM &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SYSTEM_SDHC)
return 1;
if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_RICOH &&
(PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RICOH_R5U822 ||
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RICOH_R5U823))
return 1;
return 0;
}
static void
ns16550pci_uart_probe(cfe_driver_t *drv,
unsigned long probe_a, unsigned long probe_b,
void *probe_ptr)
{
int index;
/*
* NS16550-compatible UART on the PCI bus
* probe_a, probe_b and probe_ptr are unused.
*
* This is for generic 16550-like UARTs. We use the PCI class and
* interface codes to identify compatible hardware. We require
* 16550 or better compatibility. The 16{6,7,8,9}50 parts are
* claimed to be 16550 compatible but are as yet untested.
*/
for (index = 0; ; index++) {
pcitag_t tag;
pcireg_t cr;
phys_addr_t pa;
if (pci_find_class(PCI_CLASS_COMMUNICATIONS, index, &tag) != 0) {
break;
}
cr = pci_conf_read(tag, PCI_CLASS_REG);
if (PCI_SUBCLASS(cr) == PCI_SUBCLASS_COMMUNICATIONS_SERIAL
&& PCI_INTERFACE(cr) >= 0x02 /* 16550 .. */
&& PCI_INTERFACE(cr) <= 0x06) { /* 16950 */
if (pci_map_io(tag, PCI_MAPREG(0), PCI_MATCH_BYTES, &pa) == 0)
ns16550_uart_probe(drv, pa, 0, NULL);
}
}
}
int
pcibmatch(struct device *parent, void *match, void *aux)
{
struct pci_attach_args *pa = aux;
switch (PCI_VENDOR(pa->pa_id)) {
case PCI_VENDOR_INTEL:
switch (PCI_PRODUCT(pa->pa_id)) {
case PCI_PRODUCT_INTEL_SIO:
case PCI_PRODUCT_INTEL_82371MX:
case PCI_PRODUCT_INTEL_82371AB_ISA:
case PCI_PRODUCT_INTEL_82440MX_ISA:
/* The above bridges mis-identify themselves */
return (1);
}
case PCI_VENDOR_SIS:
switch (PCI_PRODUCT(pa->pa_id)) {
case PCI_PRODUCT_SIS_85C503:
/* mis-identifies itself as a miscellaneous prehistoric */
return (1);
}
case PCI_VENDOR_VIATECH:
switch (PCI_PRODUCT(pa->pa_id)) {
case PCI_PRODUCT_VIATECH_VT82C686A_SMB:
/* mis-identifies itself as a ISA bridge */
return (0);
}
}
if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA)
return (1);
return (0);
}
static void
jmahci_attach(device_t parent, device_t self, void *aux)
{
struct jmahci_attach_args *jma = aux;
const struct pci_attach_args *pa = jma->jma_pa;
struct ahci_softc *sc = device_private(self);
uint32_t ahci_cap;
aprint_naive(": AHCI disk controller\n");
aprint_normal("\n");
sc->sc_atac.atac_dev = self;
sc->sc_ahcit = jma->jma_ahcit;
sc->sc_ahcih = jma->jma_ahcih;
ahci_cap = AHCI_READ(sc, AHCI_CAP);
if (pci_dma64_available(jma->jma_pa) && (ahci_cap & AHCI_CAP_64BIT))
sc->sc_dmat = jma->jma_pa->pa_dmat64;
else
sc->sc_dmat = jma->jma_pa->pa_dmat;
if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
sc->sc_atac_capflags = ATAC_CAP_RAID;
ahci_attach(sc);
if (!pmf_device_register(self, NULL, jmahci_resume))
aprint_error_dev(self, "couldn't establish power handler\n");
}
static int
via_pcib_match(const struct pci_attach_args *pa)
{
if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA &&
PCI_VENDOR(pa->pa_id) == PCI_VENDOR_VIATECH)
return (1);
return 0;
}
int
pchbmatch(struct device *parent, void *match, void *aux)
{
struct pci_attach_args *pa = aux;
if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_HOST)
return (1);
return (0);
}
static int
gcscide_match(device_t parent, cfdata_t cfdata, void *aux)
{
struct pci_attach_args *pa = (struct pci_attach_args *)aux;
if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS &&
PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE &&
pciide_lookup_product(pa->pa_id, pciide_gcscide_products))
return 2;
return 0;
}
static int
uhci_cardbus_match(device_t parent, cfdata_t match, void *aux)
{
struct cardbus_attach_args *ca = (struct cardbus_attach_args *)aux;
if (PCI_CLASS(ca->ca_class) == PCI_CLASS_SERIALBUS &&
PCI_SUBCLASS(ca->ca_class) == PCI_SUBCLASS_SERIALBUS_USB &&
PCI_INTERFACE(ca->ca_class) == PCI_INTERFACE_UHCI)
return 1;
return 0;
}
int
uhci_cardbus_match(struct device *parent, void *match, void *aux)
{
struct cardbus_attach_args *ca = (struct cardbus_attach_args *)aux;
if (PCI_CLASS(ca->ca_class) == PCI_CLASS_SERIALBUS &&
PCI_SUBCLASS(ca->ca_class) == PCI_SUBCLASS_SERIALBUS_USB &&
PCI_INTERFACE(ca->ca_class) == PCI_INTERFACE_UHCI)
return (1);
return (0);
}
static void
ahci_pci_attach(device_t parent, device_t self, void *aux)
{
struct pci_attach_args *pa = aux;
struct ahci_pci_softc *psc = device_private(self);
struct ahci_softc *sc = &psc->ah_sc;
bus_size_t size;
char devinfo[256];
const char *intrstr;
pci_intr_handle_t intrhandle;
void *ih;
sc->sc_atac.atac_dev = self;
if (pci_mapreg_map(pa, AHCI_PCI_ABAR,
PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
&sc->sc_ahcit, &sc->sc_ahcih, NULL, &size) != 0) {
aprint_error_dev(self, "can't map ahci registers\n");
return;
}
psc->sc_pc = pa->pa_pc;
psc->sc_pcitag = pa->pa_tag;
pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo));
aprint_naive(": AHCI disk controller\n");
aprint_normal(": %s\n", devinfo);
if (pci_intr_map(pa, &intrhandle) != 0) {
aprint_error("%s: couldn't map interrupt\n", AHCINAME(sc));
return;
}
intrstr = pci_intr_string(pa->pa_pc, intrhandle);
ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, ahci_intr, sc);
if (ih == NULL) {
aprint_error("%s: couldn't establish interrupt", AHCINAME(sc));
return;
}
aprint_normal("%s: interrupting at %s\n", AHCINAME(sc),
intrstr ? intrstr : "unknown interrupt");
sc->sc_dmat = pa->pa_dmat;
if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) {
AHCIDEBUG_PRINT(("%s: RAID mode\n", AHCINAME(sc)), DEBUG_PROBE);
sc->sc_atac_capflags = ATAC_CAP_RAID;
} else {
AHCIDEBUG_PRINT(("%s: SATA mode\n", AHCINAME(sc)), DEBUG_PROBE);
}
ahci_attach(sc);
if (!pmf_device_register(self, NULL, ahci_pci_resume))
aprint_error_dev(self, "couldn't establish power handler\n");
}
static int
hdaudio_pci_match(device_t parent, cfdata_t match, void *opaque)
{
struct pci_attach_args *pa = opaque;
if (PCI_CLASS(pa->pa_class) != PCI_CLASS_MULTIMEDIA)
return 0;
if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MULTIMEDIA_HDAUDIO)
return 0;
return 10;
}
int
ohci_pci_match(struct device *parent, void *match, void *aux)
{
struct pci_attach_args *pa = (struct pci_attach_args *) aux;
if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB &&
PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_OHCI)
return (1);
return (0);
}
static int
uhci_pci_match(device_t parent, cfdata_t match, void *aux)
{
struct pci_attach_args *pa = (struct pci_attach_args *) aux;
if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SERIALBUS &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SERIALBUS_USB &&
PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_UHCI)
return (1);
return (0);
}
static void
pci_print_func(struct pci_func *f)
{
const char *class = pci_class[0];
if (PCI_CLASS(f->dev_class) < sizeof(pci_class) / sizeof(pci_class[0]))
class = pci_class[PCI_CLASS(f->dev_class)];
printf("pci: %02x:%02x.%d: %04x:%04x: class: %x.%x (%s) irq: %d\n",
f->bus->busno, f->dev, f->func,
PCI_VENDOR(f->dev_id), PCI_PRODUCT(f->dev_id),
PCI_CLASS(f->dev_class), PCI_SUBCLASS(f->dev_class), class,
f->irq_line);
}
static int
optiide_match(device_t parent, cfdata_t match, void *aux)
{
struct pci_attach_args *pa = aux;
if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_OPTI &&
PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) {
if (pciide_lookup_product(pa->pa_id, pciide_opti_products))
return (2);
}
return (0);
}
static int
geodeide_match(device_t parent, cfdata_t match, void *aux)
{
struct pci_attach_args *pa = aux;
if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CYRIX ||
PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS) &&
PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE &&
pciide_lookup_product(pa->pa_id, pciide_geode_products))
return(2);
return (0);
}
static void
piixsata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
{
struct pciide_channel *cp;
pcireg_t interface, cmdsts;
int channel;
if (pciide_chipen(sc, pa) == 0)
return;
aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
"bus-master DMA support present");
pciide_mapreg_dma(sc, pa);
aprint_verbose("\n");
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
if (sc->sc_dma_ok) {
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
sc->sc_wdcdev.irqack = pciide_irqack;
/* Do all revisions require DMA alignment workaround? */
sc->sc_wdcdev.dma_init = piix_dma_init;
sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
}
sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
sc->sc_wdcdev.wdc_maxdrives = 2;
cmdsts = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
cmdsts &= ~PCI_COMMAND_INTERRUPT_DISABLE;
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, cmdsts);
if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID)
sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_RAID;
interface = PCI_INTERFACE(pa->pa_class);
wdc_allocate_regs(&sc->sc_wdcdev);
for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
channel++) {
cp = &sc->pciide_channels[channel];
if (pciide_chansetup(sc, channel, interface) == 0)
continue;
pciide_mapchan(pa, cp, interface, pciide_pci_intr);
}
}
static int
sdhc_pci_match(device_t parent, cfdata_t cf, void *aux)
{
struct pci_attach_args *pa = aux;
if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SYSTEM &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SYSTEM_SDHC)
return (1);
if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_RICOH &&
(PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RICOH_Rx5U822 ||
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RICOH_Rx5U823))
return (1);
return (0);
}
static int
acer_pcib_match(const struct pci_attach_args *pa)
{
/*
* we need to access the PCI config space of the pcib, see
* acer_do_reset()
*/
if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA &&
PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI &&
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M1533)
return 1;
return 0;
}
int
pcmbmatch(device_t parent, cfdata_t match, void *aux)
{
struct pci_attach_args *pa = aux;
/*
* Match anything which claims to be PCI-MCA bridge.
*/
if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE
&& PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_MC)
return (1);
return (0);
}
int
gscpcib_match(struct device *parent, void *match, void *aux)
{
struct pci_attach_args *pa = aux;
if (PCI_CLASS(pa->pa_class) != PCI_CLASS_BRIDGE ||
PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_BRIDGE_ISA)
return (0);
if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS &&
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NS_SC1100_ISA)
return (2); /* supersede pcib(4) */
return (0);
}
int
pchbmatch(struct device *parent, struct cfdata *cf, void *aux)
{
struct pci_attach_args *pa = aux;
/*
* Match all known PCI host chipsets.
*/
if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_HOST) {
return (1);
}
return (0);
}
static void
cmd680_channel_map(struct pci_attach_args *pa, struct pciide_softc *sc,
int channel)
{
struct pciide_channel *cp = &sc->pciide_channels[channel];
bus_size_t cmdsize, ctlsize;
int interface, i, reg;
static const u_int8_t init_val[] =
{ 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32,
0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 };
if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) {
interface = PCIIDE_INTERFACE_SETTABLE(0) |
PCIIDE_INTERFACE_SETTABLE(1);
interface |= PCIIDE_INTERFACE_PCI(0) |
PCIIDE_INTERFACE_PCI(1);
} else {
interface = PCI_INTERFACE(pa->pa_class);
}
sc->wdc_chanarray[channel] = &cp->wdc_channel;
cp->name = PCIIDE_CHANNEL_NAME(channel);
cp->wdc_channel.ch_channel = channel;
cp->wdc_channel.ch_wdc = &sc->sc_wdcdev;
cp->wdc_channel.ch_queue =
malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT);
if (cp->wdc_channel.ch_queue == NULL) {
aprint_error("%s %s channel: "
"can't allocate memory for command queue",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
return;
}
/* XXX */
reg = 0xa2 + channel * 16;
for (i = 0; i < sizeof(init_val); i++)
pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]);
aprint_normal("%s: %s channel %s to %s mode\n",
sc->sc_wdcdev.sc_dev.dv_xname, cp->name,
(interface & PCIIDE_INTERFACE_SETTABLE(channel)) ?
"configured" : "wired",
(interface & PCIIDE_INTERFACE_PCI(channel)) ?
"native-PCI" : "compatibility");
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, pciide_pci_intr);
}
static int
joy_pci_match(device_t parent, cfdata_t match, void *aux)
{
struct pci_attach_args *pa = aux;
if (PCI_CLASS(pa->pa_class) == PCI_CLASS_INPUT &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_INPUT_GAMEPORT &&
PCI_INTERFACE(pa->pa_class) == 0x10)
return 1;
if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CREATIVELABS &&
(PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CREATIVELABS_SBJOY ||
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CREATIVELABS_SBJOY2))
return 1;
return 0;
}
static int
iop_pci_match(struct device *parent, struct cfdata *match,
void *aux)
{
struct pci_attach_args *pa;
u_int product, vendor;
pcireg_t reg;
pa = aux;
/*
* Look for an "intelligent I/O processor" that adheres to the I2O
* specification. Ignore the device if it doesn't support interrupt
* driven operation.
*/
if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_I2O_STANDARD &&
PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_I2O_INTRDRIVEN)
return (1);
/*
* Match boards that don't conform exactly to the spec.
*/
vendor = PCI_VENDOR(pa->pa_id);
product = PCI_PRODUCT(pa->pa_id);
if (vendor == PCI_VENDOR_DPT &&
(product == PCI_PRODUCT_DPT_RAID_I2O ||
product == PCI_PRODUCT_DPT_RAID_2005S))
return (1);
if (vendor == PCI_VENDOR_INTEL &&
(product == PCI_PRODUCT_INTEL_80960RM_2 ||
product == PCI_PRODUCT_INTEL_80960_RP)) {
reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
if (PCI_VENDOR(reg) == PCI_VENDOR_PROMISE)
return (1);
}
return (0);
}
static int
pchb_match(struct device *parent, struct cfdata *match, void *aux)
{
struct pci_attach_args *pa = aux;
/*
* Match all known PCI host chipsets.
*/
if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_HOST) {
switch (PCI_VENDOR(pa->pa_id)) {
case PCI_VENDOR_GALILEO:
switch (PCI_PRODUCT(pa->pa_id)) {
case PCI_PRODUCT_GALILEO_GT64120:
return (!pcifound);
}
break;
}
}
return (0);
}
