UINT32 brdDeConfigCpciBackplane (void *ptr)
{
(void)ptr;
PCI_PFA pfa;
pfa = PCI_MAKE_PFA (0, 28, 4);
PCI_WRITE_BYTE (pfa, PCI_PRI_BUS_NUM, 0);
PCI_WRITE_BYTE (pfa, PCI_SEC_BUS_NUM, 0);
PCI_WRITE_BYTE (pfa, PCI_SUB_BUS_NUM, 0);
return (E__OK);
}
UINT32 brdConfigCpciBackplane (void *ptr)
{
PCI_PFA pfa;
char buffer[80];
(void)ptr;
pfa = PCI_MAKE_PFA (0, 28, 4);
/* To make the other boards connected via backplane visible in soak mode. */
PCI_WRITE_BYTE (pfa, PCI_PRI_BUS_NUM, 0);
PCI_WRITE_BYTE (pfa, PCI_SEC_BUS_NUM, 0x22);
PCI_WRITE_BYTE (pfa, PCI_SUB_BUS_NUM, 0x23);
pfa = PCI_MAKE_PFA (0x22, 0, 0);
*((PCI_PFA*)ptr) = pfa;
return (E__OK);
}
UINT32 brdSMBUSinfo(void *ptr)
{
PCI_PFA pfa;
UINT16 temp;
pfa = PCI_MAKE_PFA (localSMBUS.Bus, localSMBUS.Device, localSMBUS.Function);
localSMBUS.GPIOBase = PCI_READ_DWORD (pfa, localSMBUS.GPIOBaseReg);
localSMBUS.GPIOBase &= ~0x00000001;
temp = PCI_READ_WORD (pfa, 0x04);
PCI_WRITE_WORD (pfa, 0x04, (temp | 0x01));
PCI_WRITE_BYTE (pfa, 0x40, 0x01);
*((SMBUS_INFO**)ptr) = &localSMBUS;
return E__OK;
}
void
Permedia3PreInit(ScrnInfoPtr pScrn)
{
GLINTPtr pGlint = GLINTPTR(pScrn);
CARD32 LocalMemCaps;
TRACE_ENTER("Permedia3PreInit");
if (IS_J2000) {
unsigned char m,n,p;
if (pGlint->Chipset == PCI_VENDOR_3DLABS_CHIP_GAMMA)
GLINT_SLOW_WRITE_REG(GCSRSecondaryGLINTMapEn, GCSRAperture);
/* Memory timings for the Appian J2000 board.
* This is needed for the second head which is left un-initialized
* by the bios, thus freezing the machine. */
GLINT_SLOW_WRITE_REG(0x02e311B8, PM3LocalMemCaps);
GLINT_SLOW_WRITE_REG(0x07424905, PM3LocalMemTimings);
GLINT_SLOW_WRITE_REG(0x0c000003, PM3LocalMemControl);
GLINT_SLOW_WRITE_REG(0x00000061, PM3LocalMemRefresh);
GLINT_SLOW_WRITE_REG(0x00000000, PM3LocalMemPowerDown);
/* Let's program the K, M and S Clocks to the same values as the bios
* does for first head :
* - KClk and MClk are 105Mhz.
* - S Clock is set to PClk.
* Note 1 : pGlint->RefClock is not set yet, so use 14318 instead.
* Note 2 : KClk gets internally halved, so we need to double it.
*/
(void) PM3DAC_CalculateClock(2*105000, 14318, &m,&n,&p);
Permedia2vOutIndReg(pScrn, PM3RD_KClkPreScale, 0x00, m);
Permedia2vOutIndReg(pScrn, PM3RD_KClkFeedbackScale, 0x00, n);
Permedia2vOutIndReg(pScrn, PM3RD_KClkPostScale, 0x00, p);
Permedia2vOutIndReg(pScrn, PM3RD_KClkControl, 0x00,
PM3RD_KClkControl_STATE_RUN |
PM3RD_KClkControl_SOURCE_PLL |
PM3RD_KClkControl_ENABLE);
Permedia2vOutIndReg(pScrn, PM3RD_MClkControl, 0x00,
PM3RD_MClkControl_STATE_RUN |
PM3RD_MClkControl_SOURCE_KCLK |
PM3RD_MClkControl_ENABLE);
Permedia2vOutIndReg(pScrn, PM3RD_SClkControl, 0x00,
PM3RD_SClkControl_STATE_RUN |
PM3RD_SClkControl_SOURCE_PCLK |
PM3RD_SClkControl_ENABLE);
}
#if defined(__alpha__)
/*
* On Alpha, we have to "int10" secondary VX1 cards early;
* otherwise, some information taken from registers, like
* memory size, is incorrect.
*/
if (!xf86IsPrimaryPci(pGlint->PciInfo)) {
if ( IS_QVX1 ) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"VX1 secondary enabling VGA before int10\n");
/* Enable VGA on the current card. */
PCI_WRITE_BYTE(pGlint->PciInfo, 0, 0xf8);
PCI_WRITE_BYTE(pGlint->PciInfo, 0, 0xf4);
PCI_WRITE_BYTE(pGlint->PciInfo, 0, 0xfc);
/* The card we are on should be VGA-enabled now, so run int10. */
if (xf86LoadSubModule(pScrn, "int10")) {
xf86Int10InfoPtr pInt;
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Initializing int10\n");
pInt = xf86InitInt10(pGlint->pEnt->index);
xf86FreeInt10(pInt);
}
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"VX1 secondary disabling VGA after int10\n");
/* Finally, disable VGA on the current card. */
PCI_WRITE_BYTE(pGlint->PciInfo, 0x70, 0xf8);
PCI_WRITE_BYTE(pGlint->PciInfo, 0x01, 0xf4);
PCI_WRITE_BYTE(pGlint->PciInfo, 0x00, 0xfc);
}
}
#endif /* __alpha__ */
/* If we have SDRAM instead of SGRAM, we have to do some things
differently in the FillRectSolid code. */
LocalMemCaps = GLINT_READ_REG(PM3LocalMemCaps);
pGlint->PM3_UsingSGRAM = !(LocalMemCaps & PM3LocalMemCaps_NoWriteMask);
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Using %s memory\n",
pGlint->PM3_UsingSGRAM ? "SGRAM" : "SDRAM");
TRACE_EXIT("Permedia3PreInit");
}
