/** * @brief DMA IRQ * * @param None * * @return None * * @details The DMA default IRQ, declared in startup_nuc400series.s. */ void PDMA_IRQHandler(void) { uint32_t status = PDMA_GET_INT_STATUS(); if (status & 0x1) { /* abort */ if (PDMA_GET_ABORT_STS() & 0x4) u32IsTestOver = 2; PDMA_CLR_ABORT_FLAG(PDMA_ABTF_TABORT_F_Msk); } else if (status & 0x2) { /* done */ if (PDMA_GET_TD_STS() & 0x4) u32IsTestOver = 1; PDMA_CLR_TD_FLAG(PDMA_TDF_TD_F_Msk); } else if (status & 0x400) { /* channel 2 timeout */ u32IsTestOver = 3; PDMA_CLR_TMOUT_FLAG(2); } else printf("unknown interrupt !!\n"); }
/** * @brief PDMA IRQ Handler * * @param None * * @return None * * @details ISR to handle PDMA interrupt event */ void PDMA_IRQHandler(void) { uint32_t status = PDMA_GET_INT_STATUS(); if(status & 0x1) /* abort */ { if(PDMA_GET_ABORT_STS() & 0x4) g_u32IsTestOver = 2; PDMA_CLR_ABORT_FLAG(PDMA_ABTSTS_ABTIFn_Msk); } else if(status & 0x2) /* done */ { if(PDMA_GET_TD_STS() & 0x1) g_u32IsTestOver = 1; PDMA_CLR_TD_FLAG(PDMA_TDSTS_TDIFn_Msk); } else printf("unknown interrupt !!\n"); }
/** * @brief DMA IRQ * * @param None * * @return None * * @details The DMA default IRQ, declared in startup_NUC472_442.s. */ void PDMA_IRQHandler(void) { uint32_t status = PDMA_GET_INT_STATUS(); if (status & 0x1) { /* abort */ printf("target abort interrupt !!\n"); if (PDMA_GET_ABORT_STS() & 0x4) u32IsTestOver = 2; PDMA_CLR_ABORT_FLAG(PDMA_ABTSTS_ABTIF_Msk); } else if (status & 0x2) { /* done */ if ( (PDMA_GET_TD_STS() & (1 << 0)) && (PDMA_GET_TD_STS() & (1 << 1)) ) { u32IsTestOver = 1; PDMA_CLR_TD_FLAG(PDMA_TDSTS_TDIF_Msk); } } else if (status & 0x300) { /* channel 2 timeout */ printf("timeout interrupt !!\n"); u32IsTestOver = 3; PDMA_CLR_TMOUT_FLAG(0); PDMA_CLR_TMOUT_FLAG(1); } else printf("unknown interrupt !!\n"); }
static void pdma_vec(void) { uint32_t intsts = PDMA_GET_INT_STATUS(); // Abort if (intsts & PDMA_INTSTS_ABTIF_Msk) { uint32_t abtsts = PDMA_GET_ABORT_STS(); // Clear all Abort flags PDMA_CLR_ABORT_FLAG(abtsts); while (abtsts) { int chn_id = nu_ctz(abtsts); if (dma_chn_mask & (1 << chn_id)) { struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id; if (dma_chn->handler && (dma_chn->event & DMA_EVENT_ABORT)) { dma_chn->handler(dma_chn->id, DMA_EVENT_ABORT); } } abtsts &= ~(1 << chn_id); } } // Transfer done if (intsts & PDMA_INTSTS_TDIF_Msk) { uint32_t tdsts = PDMA_GET_TD_STS(); // Clear all transfer done flags PDMA_CLR_TD_FLAG(tdsts); while (tdsts) { int chn_id = nu_ctz(tdsts); if (dma_chn_mask & (1 << chn_id)) { struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id; if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TRANSFER_DONE)) { dma_chn->handler(dma_chn->id, DMA_EVENT_TRANSFER_DONE); } } tdsts &= ~(1 << chn_id); } } // Table empty if (intsts & PDMA_INTSTS_TEIF_Msk) { uint32_t scatsts = PDMA_GET_EMPTY_STS(); // Clear all table empty flags PDMA_CLR_EMPTY_FLAG(scatsts); } // Timeout uint32_t reqto = intsts & PDMA_INTSTS_REQTOFn_Msk; if (reqto) { // Clear all Timeout flags PDMA->INTSTS = reqto; while (reqto) { int chn_id = nu_ctz(reqto) - PDMA_INTSTS_REQTOFn_Pos; if (dma_chn_mask & (1 << chn_id)) { struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id; if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TIMEOUT)) { dma_chn->handler(dma_chn->id, DMA_EVENT_TIMEOUT); } } reqto &= ~(1 << (chn_id + PDMA_INTSTS_REQTOFn_Pos)); } } }