/**
* MSR write handler for Hyper-V.
*
* @returns Strict VBox status code like CPUMSetGuestMsr().
* @retval VINF_CPUM_R3_MSR_WRITE
* @retval VERR_CPUM_RAISE_GP_0
*
* @param pVCpu Pointer to the VMCPU.
* @param idMsr The MSR being written.
* @param pRange The range this MSR belongs to.
* @param uRawValue The raw value with the ignored bits not masked.
*/
VMM_INT_DECL(VBOXSTRICTRC) gimHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue)
{
NOREF(pRange);
PVM pVM = pVCpu->CTX_SUFF(pVM);
PGIMHV pHv = &pVM->gim.s.u.Hv;
switch (idMsr)
{
case MSR_GIM_HV_TPR:
PDMApicWriteMSR(pVM, pVCpu->idCpu, 0x80, uRawValue);
return VINF_SUCCESS;
case MSR_GIM_HV_EOI:
PDMApicWriteMSR(pVM, pVCpu->idCpu, 0x0B, uRawValue);
return VINF_SUCCESS;
case MSR_GIM_HV_ICR:
PDMApicWriteMSR(pVM, pVCpu->idCpu, 0x30, uRawValue);
return VINF_SUCCESS;
case MSR_GIM_HV_GUEST_OS_ID:
{
#ifndef IN_RING3
return VINF_CPUM_R3_MSR_WRITE;
#else
/* Disable the hypercall-page if 0 is written to this MSR. */
if (!uRawValue)
{
gimR3HvDisableHypercallPage(pVM);
pHv->u64HypercallMsr &= ~MSR_GIM_HV_HYPERCALL_ENABLE_BIT;
}
else
{
LogRel(("GIM: HyperV: Guest OS reported ID %#RX64\n", uRawValue));
LogRel(("GIM: HyperV: Open-source=%RTbool Vendor=%#x OS=%#x (%s) Major=%u Minor=%u ServicePack=%u Build=%u\n",
MSR_GIM_HV_GUEST_OS_ID_IS_OPENSOURCE(uRawValue), MSR_GIM_HV_GUEST_OS_ID_VENDOR(uRawValue),
MSR_GIM_HV_GUEST_OS_ID_OS_VARIANT(uRawValue), gimHvGetGuestOsIdVariantName(uRawValue),
MSR_GIM_HV_GUEST_OS_ID_MAJOR_VERSION(uRawValue), MSR_GIM_HV_GUEST_OS_ID_MINOR_VERSION(uRawValue),
MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(uRawValue), MSR_GIM_HV_GUEST_OS_ID_BUILD(uRawValue)));
}
pHv->u64GuestOsIdMsr = uRawValue;
return VINF_SUCCESS;
#endif /* IN_RING3 */
}
case MSR_GIM_HV_HYPERCALL:
{
#ifndef IN_RING3
return VINF_CPUM_R3_MSR_WRITE;
#else /* IN_RING3 */
/*
* For now ignore writes to the hypercall MSR (i.e. keeps it disabled).
* This is required to boot FreeBSD 10.1 (with Hyper-V enabled ofc),
* see @bugref{7270#c116}.
*/
return VINF_SUCCESS;
# if 0
/* First, update all but the hypercall enable bit. */
pHv->u64HypercallMsr = (uRawValue & ~MSR_GIM_HV_HYPERCALL_ENABLE_BIT);
/* Hypercalls can only be enabled when the guest has set the Guest-OS Id Msr. */
bool fEnable = RT_BOOL(uRawValue & MSR_GIM_HV_HYPERCALL_ENABLE_BIT);
if ( fEnable
&& !pHv->u64GuestOsIdMsr)
{
return VINF_SUCCESS;
}
/* Is the guest disabling the hypercall-page? Allow it regardless of the Guest-OS Id Msr. */
if (!fEnable)
{
gimR3HvDisableHypercallPage(pVM);
pHv->u64HypercallMsr = uRawValue;
return VINF_SUCCESS;
}
/* Enable the hypercall-page. */
RTGCPHYS GCPhysHypercallPage = MSR_GIM_HV_HYPERCALL_GUEST_PFN(uRawValue) << PAGE_SHIFT;
int rc = gimR3HvEnableHypercallPage(pVM, GCPhysHypercallPage);
if (RT_SUCCESS(rc))
{
pHv->u64HypercallMsr = uRawValue;
return VINF_SUCCESS;
}
return VERR_CPUM_RAISE_GP_0;
# endif
#endif /* IN_RING3 */
}
case MSR_GIM_HV_REF_TSC:
{
#ifndef IN_RING3
return VINF_CPUM_R3_MSR_WRITE;
#else /* IN_RING3 */
/* First, update all but the TSC-page enable bit. */
pHv->u64TscPageMsr = (uRawValue & ~MSR_GIM_HV_REF_TSC_ENABLE_BIT);
/* Is the guest disabling the TSC-page? */
bool fEnable = RT_BOOL(uRawValue & MSR_GIM_HV_REF_TSC_ENABLE_BIT);
if (!fEnable)
{
gimR3HvDisableTscPage(pVM);
pHv->u64TscPageMsr = uRawValue;
return VINF_SUCCESS;
}
/* Enable the TSC-page. */
RTGCPHYS GCPhysTscPage = MSR_GIM_HV_REF_TSC_GUEST_PFN(uRawValue) << PAGE_SHIFT;
int rc = gimR3HvEnableTscPage(pVM, GCPhysTscPage, false /* fUseThisTscSequence */, 0 /* uTscSequence */);
if (RT_SUCCESS(rc))
{
pHv->u64TscPageMsr = uRawValue;
return VINF_SUCCESS;
}
return VERR_CPUM_RAISE_GP_0;
#endif /* IN_RING3 */
}
case MSR_GIM_HV_RESET:
{
#ifndef IN_RING3
return VINF_CPUM_R3_MSR_WRITE;
#else
if (MSR_GIM_HV_RESET_IS_SET(uRawValue))
{
LogRel(("GIM: HyperV: Reset initiated through MSR\n"));
int rc = PDMDevHlpVMReset(pVM->gim.s.pDevInsR3);
AssertRC(rc);
}
/* else: Ignore writes to other bits. */
return VINF_SUCCESS;
#endif /* IN_RING3 */
}
case MSR_GIM_HV_CRASH_CTL:
{
#ifndef IN_RING3
return VINF_CPUM_R3_MSR_WRITE;
#else
if (uRawValue & MSR_GIM_HV_CRASH_CTL_NOTIFY_BIT)
{
LogRel(("GIM: HyperV: Guest indicates a fatal condition! P0=%#RX64 P1=%#RX64 P2=%#RX64 P3=%#RX64 P4=%#RX64\n",
pHv->uCrashP0, pHv->uCrashP1, pHv->uCrashP2, pHv->uCrashP3, pHv->uCrashP4));
}
return VINF_SUCCESS;
#endif
}
case MSR_GIM_HV_CRASH_P0: pHv->uCrashP0 = uRawValue; return VINF_SUCCESS;
case MSR_GIM_HV_CRASH_P1: pHv->uCrashP1 = uRawValue; return VINF_SUCCESS;
case MSR_GIM_HV_CRASH_P2: pHv->uCrashP2 = uRawValue; return VINF_SUCCESS;
case MSR_GIM_HV_CRASH_P3: pHv->uCrashP3 = uRawValue; return VINF_SUCCESS;
case MSR_GIM_HV_CRASH_P4: pHv->uCrashP4 = uRawValue; return VINF_SUCCESS;
case MSR_GIM_HV_TIME_REF_COUNT: /* Read-only MSRs. */
case MSR_GIM_HV_VP_INDEX:
case MSR_GIM_HV_TSC_FREQ:
case MSR_GIM_HV_APIC_FREQ:
LogFunc(("WrMsr on read-only MSR %#RX32 -> #GP(0)\n", idMsr));
return VERR_CPUM_RAISE_GP_0;
default:
{
#ifdef IN_RING3
static uint32_t s_cTimes = 0;
if (s_cTimes++ < 20)
LogRel(("GIM: HyperV: Unknown/invalid WrMsr (%#x,%#x`%08x) -> #GP(0)\n", idMsr,
uRawValue & UINT64_C(0xffffffff00000000), uRawValue & UINT64_C(0xffffffff)));
#endif
LogFunc(("Unknown/invalid WrMsr (%#RX32,%#RX64) -> #GP(0)\n", idMsr, uRawValue));
break;
}
}
return VERR_CPUM_RAISE_GP_0;
}
static int kbd_write_command(void *opaque, uint32_t addr, uint32_t val)
{
int rc = VINF_SUCCESS;
KBDState *s = (KBDState*)opaque;
NOREF(addr);
#ifdef DEBUG_KBD
Log(("kbd: write cmd=0x%02x\n", val));
#endif
switch(val) {
case KBD_CCMD_READ_MODE:
kbc_dbb_out(s, s->mode);
break;
case KBD_CCMD_WRITE_MODE:
case KBD_CCMD_WRITE_OBUF:
case KBD_CCMD_WRITE_AUX_OBUF:
case KBD_CCMD_WRITE_MOUSE:
case KBD_CCMD_WRITE_OUTPORT:
s->write_cmd = val;
break;
case KBD_CCMD_MOUSE_DISABLE:
s->mode |= KBD_MODE_DISABLE_MOUSE;
break;
case KBD_CCMD_MOUSE_ENABLE:
s->mode &= ~KBD_MODE_DISABLE_MOUSE;
/* Check for queued input. */
kbd_update_irq(s);
break;
case KBD_CCMD_TEST_MOUSE:
kbc_dbb_out(s, 0x00);
break;
case KBD_CCMD_SELF_TEST:
/* Enable the A20 line - that is the power-on state(!). */
# ifndef IN_RING3
if (!PDMDevHlpA20IsEnabled(s->CTX_SUFF(pDevIns)))
{
rc = VINF_IOM_R3_IOPORT_WRITE;
break;
}
# else /* IN_RING3 */
PDMDevHlpA20Set(s->CTX_SUFF(pDevIns), true);
# endif /* IN_RING3 */
s->status |= KBD_STAT_SELFTEST;
s->mode |= KBD_MODE_DISABLE_KBD;
kbc_dbb_out(s, 0x55);
break;
case KBD_CCMD_KBD_TEST:
kbc_dbb_out(s, 0x00);
break;
case KBD_CCMD_KBD_DISABLE:
s->mode |= KBD_MODE_DISABLE_KBD;
break;
case KBD_CCMD_KBD_ENABLE:
s->mode &= ~KBD_MODE_DISABLE_KBD;
/* Check for queued input. */
kbd_update_irq(s);
break;
case KBD_CCMD_READ_INPORT:
kbc_dbb_out(s, 0xBF);
break;
case KBD_CCMD_READ_OUTPORT:
/* XXX: check that */
#ifdef TARGET_I386
val = 0x01 | (PDMDevHlpA20IsEnabled(s->CTX_SUFF(pDevIns)) << 1);
#else
val = 0x01;
#endif
if (s->status & KBD_STAT_OBF)
val |= 0x10;
if (s->status & KBD_STAT_MOUSE_OBF)
val |= 0x20;
kbc_dbb_out(s, val);
break;
#ifdef TARGET_I386
case KBD_CCMD_ENABLE_A20:
# ifndef IN_RING3
if (!PDMDevHlpA20IsEnabled(s->CTX_SUFF(pDevIns)))
rc = VINF_IOM_R3_IOPORT_WRITE;
# else /* IN_RING3 */
PDMDevHlpA20Set(s->CTX_SUFF(pDevIns), true);
# endif /* IN_RING3 */
break;
case KBD_CCMD_DISABLE_A20:
# ifndef IN_RING3
if (PDMDevHlpA20IsEnabled(s->CTX_SUFF(pDevIns)))
rc = VINF_IOM_R3_IOPORT_WRITE;
# else /* IN_RING3 */
PDMDevHlpA20Set(s->CTX_SUFF(pDevIns), false);
# endif /* !IN_RING3 */
break;
#endif
case KBD_CCMD_READ_TSTINP:
/* Keyboard clock line is zero IFF keyboard is disabled */
val = (s->mode & KBD_MODE_DISABLE_KBD) ? 0 : 1;
kbc_dbb_out(s, val);
break;
case KBD_CCMD_RESET:
case KBD_CCMD_RESET_ALT:
#ifndef IN_RING3
rc = VINF_IOM_R3_IOPORT_WRITE;
#else /* IN_RING3 */
LogRel(("Reset initiated by keyboard controller\n"));
rc = PDMDevHlpVMReset(s->CTX_SUFF(pDevIns), PDMVMRESET_F_KBD);
#endif /* !IN_RING3 */
break;
case 0xff:
/* ignore that - I don't know what is its use */
break;
/* Make OS/2 happy. */
/* The 8042 RAM is readable using commands 0x20 thru 0x3f, and writable
by 0x60 thru 0x7f. Now days only the first byte, the mode, is used.
We'll ignore the writes (0x61..7f) and return 0 for all the reads
just to make some OS/2 debug stuff a bit happier. */
case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f:
case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
case 0x38: case 0x39: case 0x3a: case 0x3b: case 0x3c: case 0x3d: case 0x3e: case 0x3f:
kbc_dbb_out(s, 0);
Log(("kbd: reading non-standard RAM addr %#x\n", val & 0x1f));
break;
default:
Log(("kbd: unsupported keyboard cmd=0x%02x\n", val));
break;
}
return rc;
}
