void at91_spi0_hw_init(void)
{
/* Configure the spi0 pins */
/* {"MISO", AT91C_PIN_PA(0), 0, PIO_DEFAULT, PIO_PERIPH_A}
{"MOSI", AT91C_PIN_PA(1), 0, PIO_DEFAULT, PIO_PERIPH_A}
{"SPCK", AT91C_PIN_PA(2), 0, PIO_DEFAULT, PIO_PERIPH_A}*/
writel(((0x01 << 0) | (0x01 << 1) | (0x01 << 2)), AT91C_BASE_PIOA + PIO_ASR(0));
writel(((0x01 << 0) | (0x01 << 1) | (0x01 << 2)), AT91C_BASE_PIOA + PIO_PDR(0));
#if (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS0_DATAFLASH)
/* {"NPCS", AT91C_PIN_PA(3), 1, PIO_PULLUP, PIO_OUTPUT}, */
writel((0x01 << 3), AT91C_BASE_PIOA + PIO_IDR(0));
writel((0x01 << 3), AT91C_BASE_PIOA + PIO_PPUDR(0));
writel((0x01 << 3), AT91C_BASE_PIOA + PIO_SODR(0));
writel((0x01 << 3), AT91C_BASE_PIOA + PIO_OER(0));
writel((0x01 << 3), AT91C_BASE_PIOA + PIO_PER(0));
writel((1 << AT91C_ID_PIOA), (PMC_PCER + AT91C_BASE_PMC));
#endif
#if (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS1_DATAFLASH)
/* {"NPCS", AT91C_PIN_PC(11), 1, PIO_PULLUP, PIO_OUTPUT}, */
writel((0x01 << 11), AT91C_BASE_PIOC + PIO_IDR(0));
writel((0x01 << 11), AT91C_BASE_PIOC + PIO_PPUDR(0));
writel((0x01 << 11), AT91C_BASE_PIOC + PIO_SODR(0));
writel((0x01 << 11), AT91C_BASE_PIOC + PIO_OER(0));
writel((0x01 << 11), AT91C_BASE_PIOC + PIO_PER(0));
writel(((1 << AT91C_ID_PIOA) | (1 << AT91C_ID_PIOC)), (PMC_PCER + AT91C_BASE_PMC));
#endif
/* Enable the spi0 clock */
writel((1 << AT91C_ID_SPI0), (PMC_PCER + AT91C_BASE_PMC));
}
static int ek_special_hw_init(void)
{
/*
* For on the sam9m10g45ek board, the chip wm9711 stay in the test mode,
* so it need do some action to exit mode.
*/
const struct pio_desc wm9711_pins[] = {
{"AC97TX", AT91C_PIN_PD(7), 0, PIO_PULLUP, PIO_OUTPUT},
{"AC97FS", AT91C_PIN_PD(8), 0, PIO_PULLUP, PIO_OUTPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
pio_configure(wm9711_pins);
writel((1 << AT91C_ID_PIOD_E), PMC_PCER + AT91C_BASE_PMC);
/*
* Disable pull-up on:
* RXDV(PA15) => PHY normal mode (not Test mode)
* ERX0(PA12) => PHY ADDR0
* ERX1(PA13) => PHY ADDR1 => PHYADDR = 0x0
*
* PHY has internal pull-down
*/
writel((0x01 << 12) | (0x01 << 13) | (0x01 << 15), AT91C_BASE_PIOA + PIO_PPUDR(0));
return 0;
}
static int ek_special_hw_init(void)
{
unsigned long rstc;
unsigned long rst_key = (0xA5 << 24);
/*
* For on the sam9m10g45ek board, the chip wm9711 stay in the test mode,
* so it need do some action to exit mode.
*/
const struct pio_desc wm9711_pins[] = {
{"AC97TX", AT91C_PIN_PD(7), 0, PIO_PULLUP, PIO_OUTPUT},
{"AC97FS", AT91C_PIN_PD(8), 0, PIO_PULLUP, PIO_OUTPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
pio_configure(wm9711_pins);
writel((1 << AT91C_ID_PIOD_E), PMC_PCER + AT91C_BASE_PMC);
/*
* Disable pull-up on:
* RXDV(PA15) => PHY normal mode (not Test mode)
* ERX0(PA12) => PHY ADDR0
* ERX1(PA13) => PHY ADDR1 => PHYADDR = 0x0
*
* PHY has internal pull-down
*/
writel((0x01 << 12) | (0x01 << 13) | (0x01 << 15), AT91C_BASE_PIOA + PIO_PPUDR(0));
rstc = at91_sys_read(AT91C_BASE_RSTC + RSTC_RMR);
/* Need to reset PHY -> 500ms reset */
at91_sys_write(AT91C_BASE_RSTC + RSTC_RMR, rst_key |
(AT91C_RSTC_ERSTL & (0x0D << 8)) |
AT91C_RSTC_URSTEN);
at91_sys_write(AT91C_BASE_RSTC + RSTC_RCR, rst_key | AT91C_RSTC_EXTRST);
/* Wait for end hardware reset */
while (!(at91_sys_read(AT91C_BASE_RSTC + RSTC_RSR) & AT91C_RSTC_NRSTL));
/* Restore NRST value */
at91_sys_write(AT91C_BASE_RSTC + RSTC_RMR, rst_key |
(rstc) |
AT91C_RSTC_URSTEN);
return 0;
}
void nandflash_hw_init(void)
{
unsigned int reg;
/* Setup Smart Media, first enable the address range of
* CS3 in HMATRIX user interface */
reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
reg |= AT91C_EBI_CS3A_SM;
writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
/* Configure SMC CS3 */
writel((AT91C_SMC_NWESETUP_(1)
| AT91C_SMC_NCS_WRSETUP_(0)
| AT91C_SMC_NRDSETUP_(1)
| AT91C_SMC_NCS_RDSETUP_(0)),
AT91C_BASE_SMC + SMC_SETUP3);
writel((AT91C_SMC_NWEPULSE_(3)
| AT91C_SMC_NCS_WRPULSE_(3)
| AT91C_SMC_NRDPULSE_(3)
| AT91C_SMC_NCS_RDPULSE_(3)),
AT91C_BASE_SMC + SMC_PULSE3);
writel((AT91C_SMC_NWECYCLE_(5)
| AT91C_SMC_NRDCYCLE_(5)),
AT91C_BASE_SMC + SMC_CYCLE3);
writel((AT91C_SMC_READMODE
| AT91C_SMC_WRITEMODE
/* AT91C_SMC_NWAITM_NWAIT_DISABLE */
| (0x0 << 5)
| AT91C_SMC_DBW_WIDTH_BITS_16
| AT91_SMC_TDF_(2)),
AT91C_BASE_SMC + SMC_CTRL3);
/* configure NAND pins */
/* {"NANDCS", AT91C_PIN_PC(14), 1, PIO_PULLUP, PIO_OUTPUT} */
writel((0x01 << 14), AT91C_BASE_PIOC + PIO_IDR(0));
writel((0x01 << 14), AT91C_BASE_PIOC + PIO_PPUDR(0));
writel((0x01 << 14), AT91C_BASE_PIOC + PIO_SODR(0));
writel((0x01 << 14), AT91C_BASE_PIOC + PIO_OER(0));
writel((0x01 << 14), AT91C_BASE_PIOC + PIO_PER(0));
/* enable PIOC clock */
writel((1 << AT91C_ID_PIOC), PMC_PCER + AT91C_BASE_PMC);
}
