void SAMA5D3X_ClockInit()
{
PMC_SelectExt12M_Osc();
PMC_SwitchMck2Main();
PMC_SetPllA(CKGR_PLLAR_STUCKTO1 |
CKGR_PLLAR_PLLACOUNT(0x3F) |
CKGR_PLLAR_OUTA(0x0) |
CKGR_PLLAR_MULA(65) |
CKGR_PLLAR_DIVA(1),
0x3u << 8);
PMC_SetMckPllaDiv(PMC_MCKR_PLLADIV2_DIV2);
PMC_SetMckPrescaler(PMC_MCKR_PRES_CLOCK);
PMC_SetMckDivider(PMC_MCKR_MDIV_PCK_DIV3);
PMC_SwitchMck2Pll();
}
/**
* \brief Performs the low-level initialization of the chip.
* This includes EFC and master clock configuration.
* It also enable a low level on the pin NRST triggers a user reset.
*/
extern WEAK void LowLevelInit( void )
{
uint32_t i;
if ((uint32_t)LowLevelInit < DDR_CS_ADDR) /* Code not in external mem */ {
PMC_SelectExt12M_Osc();
PMC_SwitchMck2Main();
PMC_SetPllA( CKGR_PLLAR_STUCKTO1 |
CKGR_PLLAR_PLLACOUNT(0x3F) |
CKGR_PLLAR_OUTA(0x0) |
CKGR_PLLAR_MULA(65) |
CKGR_PLLAR_DIVA(1),
0x3u << 8);
PMC_SetMckPllaDiv(PMC_MCKR_PLLADIV2_DIV2);
PMC_SetMckPrescaler(PMC_MCKR_PRES_CLOCK);
PMC_SetMckDivider(PMC_MCKR_MDIV_PCK_DIV3);
PMC_SwitchMck2Pll();
}
#if 0
uint32_t abcdsr;
/* Configure PCK1 to measure MCK */
PIOD->PIO_IDR = (1<<31);
abcdsr = PIOD->PIO_ABCDSR[0];
PIOD->PIO_ABCDSR[0] = ((1<<31) | abcdsr);
abcdsr = PIOD->PIO_ABCDSR[1];
PIOD->PIO_ABCDSR[1] &= (~(1<<31) & abcdsr);
PIOD->PIO_PDR = (1<<31);
/* Disable programmable clock 1 output */
REG_PMC_SCDR = PMC_SCER_PCK1;
/* Enable the DAC master clock */
PMC->PMC_PCK[1] = PMC_PCK_CSS_MCK_CLK | PMC_PCK_PRES_CLOCK;
/* Enable programmable clock 1 output */
REG_PMC_SCER = PMC_SCER_PCK1;
/* Wait for the PCKRDY1 bit to be set in the PMC_SR register*/
while ((REG_PMC_SR & PMC_SR_PCKRDY1) == 0);
#endif
/* select FIQ */
AIC->AIC_SSR = 0;
AIC->AIC_SVR = (unsigned int) defaultFiqHandler;
for (i = 1; i < 31; i++)
{
AIC->AIC_SSR = i;
AIC->AIC_SVR = (unsigned int) defaultIrqHandler;
}
AIC->AIC_SPU = (unsigned int) defaultSpuriousHandler;
/* Disable all interrupts */
for (i = 1; i < 31; i++)
{
AIC->AIC_SSR = i;
AIC->AIC_IDCR = 1 ;
}
/* Clear All pending interrupts flags */
for (i = 1; i < 31; i++)
{
AIC->AIC_SSR = i;
AIC->AIC_ICCR = 1 ;
}
/* Perform 8 IT acknoledge (write any value in EOICR) */
for (i = 0; i < 8 ; i++)
{
AIC->AIC_EOICR = 0;
}
/* Remap */
BOARD_RemapRam();
}
