static int nand_resume(struct platform_device *pdev) { struct nxp_nand *nxp = platform_get_drvdata(pdev); struct mtd_info *mtd = &nxp->mtd; struct nand_chip *chip = mtd->priv; PM_DBGOUT("+%s\n", __func__); /* Select the device */ nand_dev_init(mtd); chip->select_chip(mtd, 0); #if defined (CONFIG_MTD_NAND_ECC_HW) nand_hw_ecc_init_device(mtd); #endif nxp_nand_timing_set(mtd); /* * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) * after power-up */ chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); PM_DBGOUT("-%s\n", __func__); return 0; }
static int nxp_backward_camera_suspend(struct device *dev) { struct nxp_backward_camera_context *me = &_context; PM_DBGOUT("+%s\n", __func__); me->running = false; PM_DBGOUT("-%s\n", __func__); return 0; }
static int nxp_backward_camera_resume(struct device *dev) { struct nxp_backward_camera_context *me = &_context; PM_DBGOUT("+%s\n", __func__); if (!me->client) _get_i2c_client(me); queue_delayed_work(system_nrt_wq, &me->resume_work, msecs_to_jiffies(RESUME_CAMERA_ON_DELAY_MS)); PM_DBGOUT("-%s\n", __func__); return 0; }
static int nx_rtc_driver_resume(struct platform_device *pdev) { PM_DBGOUT("+%s (rtc irq:%s, alarm irq:%s)\n", __func__, rtc_enable_irq?"on":"off", alm_enable_irq?"on":"off"); if(rtc_enable_irq) { NX_RTC_ClearInterruptPending(RTC_COUNT_BIT); NX_RTC_SetInterruptEnable(RTC_COUNT_BIT, CTRUE); } PM_DBGOUT("-%s\n", __func__); return 0; }
static int nxp_key_resume(struct platform_device *pdev) { struct key_info *key = platform_get_drvdata(pdev); struct key_code *code = key->code; int i = 0; PM_DBGOUT("%s\n", __func__); for (i = 0; key->keys > i; i++, code++) { if (code->keycode == KEY_POWER && CHECK_PWR_KEY_EVENT(code->io)) { int delay = key->resume_delay_ms ? key->resume_delay_ms : PWR_KEY_RESUME_DELAY; input_report_key(key->input, KEY_POWER, 1); input_sync(key->input); input_report_key(key->input, KEY_POWER, 0); input_sync(key->input); code->irq_disabled = 1; disable_irq(gpio_to_irq(code->io)); schedule_delayed_work(&key->resume_work, msecs_to_jiffies(delay)); } } return 0; }
static int es8316_resume_post(struct snd_soc_card *card) { struct snd_soc_codec *codec = es8316; int jack = jack_gpio.gpio; int invert = jack_gpio.invert; int level = gpio_get_value_cansleep(jack); PM_DBGOUT("%s BAIAS=%d, PRE=%d\n", __func__, codec->dapm.bias_level, codec_bias_level); if (!codec) return -1; if (SND_SOC_BIAS_OFF != codec_bias_level) codec->driver->resume(codec); if (invert) level = !level; pr_debug("%s: hp jack %s\n", __func__, level?"IN":"OUT"); if (!level) { es8316_jack_insert = 0; } else { es8316_jack_insert = 1; } pr_debug("%s: jack_insert %d\n", __func__, es8316_jack_insert); snd_soc_jack_report(&hp_jack, level, jack_gpio.report); return 0; }
int resume_nxp_out(struct nxp_out *me) { PM_DBGOUT("+%s\n", __func__); resume_nxp_mlc(me->mlcs[0]); resume_nxp_mlc(me->mlcs[1]); #if defined(CONFIG_NXP_OUT_RESOLUTION_CONVERTER) resume_nxp_resc(me->resc); #endif #if defined(CONFIG_NXP_OUT_HDMI) resume_nxp_hdmi(me->hdmi); #endif PM_DBGOUT("-%s\n", __func__); return 0; }
static int es8316_suspend_pre(struct snd_soc_card *card) { PM_DBGOUT("+%s\n", __func__); gpio_set_value(AUDIO_AMP_POWER, 0); return 0; }
static int nxp_pdm_dai_resume(struct snd_soc_dai *dai) { struct nxp_pdm_snd_param *par = snd_soc_dai_get_drvdata(dai); PM_DBGOUT("%s\n", __func__); pdm_reset(par); return 0; }
static int alc5623_resume_post(struct snd_soc_card *card) { struct snd_soc_codec *codec = alc5623; PM_DBGOUT("%s BAIAS=%d\n", __func__, codec->dapm.bias_level); if (SND_SOC_BIAS_OFF != codec_bias_level) codec->driver->resume(codec); alc5623_jack_status_check(); return 0; }
static void __dwmci_resume(struct dw_mci *host) { struct device *dev = &host->dev; struct dw_mci_board *brd = host->pdata; PM_DBGOUT("%s: dw_mmc.%d, %d\n", __func__, dev->id, brd->bus_hz); __dwmci_initialize(dev->id, brd->bus_hz); if (brd->late_resume) brd->late_resume(host); }
static int nxp_v4l2_resume(struct device *dev) { int ret; int i; PM_DBGOUT("+%s\n", __func__); #ifdef CONFIG_VIDEO_NXP_CAPTURE for (i = 0; i < NXP_MAX_CAPTURE_NUM; i++) { if (__me->capture[i]) { ret = resume_nxp_capture(__me->capture[i]); if (ret) { PM_DBGOUT("failed to suspend capture %d\n", i); return ret; } } } #endif #ifdef CONFIG_NXP_M2M_SCALER if (__me->scaler) { ret = resume_nxp_scaler(__me->scaler); if (ret) { PM_DBGOUT(KERN_ERR "failed to suspend scaler\n"); return ret; } } #endif #ifdef CONFIG_VIDEO_NXP_OUT if (__me->out) { ret = resume_nxp_out(__me->out); if (ret) { PM_DBGOUT(KERN_ERR "failed to suspend out\n"); return ret; } } #endif PM_DBGOUT("-%s\n", __func__); return 0; }
static int nxp_spdif_dai_resume(struct snd_soc_dai *dai) { struct nxp_spdif_snd_param *par = snd_soc_dai_get_drvdata(dai); struct spdif_register *spdif = &par->spdif; unsigned int ctrl = par->base_addr + SPDIF_CTRL_OFFSET; PM_DBGOUT("%s\n", __func__); spdif_reset(par); writel(spdif->ctrl, ctrl); return 0; }
static int lcd_enable(struct disp_process_dev *pdev, int enable) { PM_DBGOUT("%s %s, %s\n", __func__, dev_to_str(pdev->dev_id), enable?"ON":"OFF"); if (! enable) { pdev->status &= ~PROC_STATUS_ENABLE; } else { lcd_prepare(pdev); pdev->status |= PROC_STATUS_ENABLE; } return 0; }
static int nx_pcm_ops_trigger(struct snd_pcm_substream *substream, int cmd) { struct nx_runtime_data *rtd; unsigned long flags; int ret = 0; DBGOUT("%s(cmd:0x%x)\n", __func__, cmd); rtd = substream->runtime->private_data; spin_lock_irqsave(&rtd->lock, flags); switch (cmd) { case SNDRV_PCM_TRIGGER_RESUME: PM_DBGOUT("+%s\n", __func__); case SNDRV_PCM_TRIGGER_START: case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: ret = start_dma_ch(substream); if (SNDRV_PCM_TRIGGER_RESUME == cmd) PM_DBGOUT("-%s\n", __func__); break; case SNDRV_PCM_TRIGGER_SUSPEND: PM_DBGOUT("+%s\n", __func__); case SNDRV_PCM_TRIGGER_STOP: case SNDRV_PCM_TRIGGER_PAUSE_PUSH: ret = stop_dma_ch(substream); if (SNDRV_PCM_TRIGGER_RESUME == cmd) PM_DBGOUT("-%s\n", __func__); break; default: ret = -EINVAL; break; } spin_unlock_irqrestore(&rtd->lock, flags); return ret; }
static int most2120_codec_resume_pre(struct platform_device *pdev) { struct snd_soc_device *socdev = platform_get_drvdata(pdev); struct snd_soc_card *card = socdev->card; struct snd_soc_dai *cpu_dai = card->dai_link->cpu_dai; int ret = 0; PM_DBGOUT("+%s\n", __func__); /* * first execute cpu(i2s) resume and execute codec resume. */ if (cpu_dai->resume && ! cpu_dai_resume) { cpu_dai_resume = cpu_dai->resume; cpu_dai->resume = NULL; } if (cpu_dai_resume) ret = cpu_dai_resume(cpu_dai); PM_DBGOUT("-%s\n", __func__); return ret; }
static int es8316_resume_pre(struct snd_soc_card *card) { struct snd_soc_dai *cpu_dai = card->rtd->cpu_dai; struct snd_soc_codec *codec = es8316; int ret = 0; PM_DBGOUT("+%s\n", __func__); /* * first execute cpu(i2s) resume and execute codec resume. */ if (cpu_dai->driver->resume && ! cpu_resume_fn) { cpu_resume_fn = cpu_dai->driver->resume; cpu_dai->driver->resume = NULL; } if (cpu_resume_fn) ret = cpu_resume_fn(cpu_dai); PM_DBGOUT("-%s\n", __func__); codec_bias_level = codec->dapm.bias_level; return ret; }
static int alc5623_resume_pre(struct snd_soc_card *card) { struct snd_soc_dai *cpu_dai = card->rtd->cpu_dai; struct snd_soc_codec *codec = alc5623; int ret = 0; if (cpu_dai->driver->resume && ! cpu_resume_fn) { cpu_resume_fn = cpu_dai->driver->resume; cpu_dai->driver->resume = NULL; } if (cpu_resume_fn) ret = cpu_resume_fn(cpu_dai); PM_DBGOUT("%s BAIAS=%d\n", __func__, codec->dapm.bias_level); codec_bias_level = codec->dapm.bias_level; return ret; }
static void mipi_resume(struct disp_process_dev *pdev) { int index = 0; PM_DBGOUT("%s\n", __func__); NX_TIEOFF_Set(TIEOFFINDEX_OF_MIPI0_NX_DPSRAM_1R1W_EMAA, 3); NX_TIEOFF_Set(TIEOFFINDEX_OF_MIPI0_NX_DPSRAM_1R1W_EMAB, 3); if (! nxp_soc_peri_reset_status(NX_MIPI_GetResetNumber(index, NX_MIPI_RST))) { nxp_soc_peri_reset_enter(NX_MIPI_GetResetNumber(index, NX_MIPI_RST)); nxp_soc_peri_reset_enter(NX_MIPI_GetResetNumber(index, NX_MIPI_RST_DSI_I)); nxp_soc_peri_reset_enter(NX_MIPI_GetResetNumber(index, NX_MIPI_RST_PHY_S)); nxp_soc_peri_reset_enter(NX_MIPI_GetResetNumber(index, NX_MIPI_RST_PHY_M)); nxp_soc_peri_reset_exit (NX_MIPI_GetResetNumber(index, NX_MIPI_RST)); nxp_soc_peri_reset_exit (NX_MIPI_GetResetNumber(index, NX_MIPI_RST_DSI_I)); nxp_soc_peri_reset_exit (NX_MIPI_GetResetNumber(index, NX_MIPI_RST_PHY_S)); nxp_soc_peri_reset_exit (NX_MIPI_GetResetNumber(index, NX_MIPI_RST_PHY_M)); } mipi_enable(pdev, 1); }
static unsigned long i2s_ext_mclk_set_clock(unsigned long clk, int ch) { unsigned long ret_clk = 0; PM_DBGOUT("%s: %ld\n", __func__, clk); if (clk > 1) { // set input & gpio_mode of I2S MCLK pin switch (ch) { case 0: nxp_soc_gpio_set_io_func(PAD_GPIO_D + 13, NX_GPIO_PADFUNC_0); nxp_soc_gpio_set_io_dir(PAD_GPIO_D + 13, 0); break; case 1: case 2: nxp_soc_gpio_set_io_func(PAD_GPIO_A + 28, NX_GPIO_PADFUNC_0); nxp_soc_gpio_set_io_dir(PAD_GPIO_A + 28, 0); break; default: break; } #if defined(CFG_EXT_MCLK_PWM_CH) nxp_cpu_periph_clock_register(CLK_ID_I2S_0 + ch, clk, 0); i2s_ext_clk_value = clk; } else { if (clk) { ret_clk = nxp_soc_pwm_set_frequency(CFG_EXT_MCLK_PWM_CH, i2s_ext_clk_value, 50); } else { ret_clk = nxp_soc_pwm_set_frequency(CFG_EXT_MCLK_PWM_CH, 0, 0); } } msleep(1); #else printk("err!!! must have other ext_clk++\n"); nxp_cpu_periph_clock_register(CLK_ID_I2S_0 + ch, clk, 0); i2s_ext_clk_value = clk; } else {
void otg_phy_off(void) { PM_DBGOUT("+%s\n", __func__); // 0. Select VBUS writel(readl(SOC_VA_TIEOFF + 0x34) | (3<<24), SOC_VA_TIEOFF + 0x34); /* Select VBUS 3.3V */ // writel(readl(SOC_VA_TIEOFF + 0x34) & ~(3<<24), SOC_VA_TIEOFF + 0x34); /* Select VBUS 5V */ // 1. UTMI reset writel(readl(SOC_VA_TIEOFF + 0x34) & ~(1<<3), SOC_VA_TIEOFF + 0x34); udelay(10); // 10 clock need // 2. AHB reset writel(readl(SOC_VA_TIEOFF + 0x34) & ~(1<<2), SOC_VA_TIEOFF + 0x34); udelay(10); // 10 clock need // 3. POR of PHY writel(readl(SOC_VA_TIEOFF + 0x34) | (3<<7), SOC_VA_TIEOFF + 0x34); udelay(10); // 40us delay need. // 4. Release otg common reset writel(readl(SOC_VA_RSTCON + 0x04) & ~(1<<25), SOC_VA_RSTCON + 0x04); // reset on udelay(10); }
int suspend_nxp_out(struct nxp_out *me) { int ret; PM_DBGOUT("+%s\n", __func__); #if defined(CONFIG_NXP_OUT_HDMI) ret = suspend_nxp_hdmi(me->hdmi); if (ret) { PM_DBGOUT("%s: failed to suspend_nxp_hdmi, ret %d\n", __func__, ret); return ret; } #endif #if defined(CONFIG_NXP_OUT_RESOLUTION_CONVERTER) ret = suspend_nxp_resc(me->resc); if (ret) { PM_DBGOUT("%s: failed to suspend_nxp_resc, ret %d\n", __func__, ret); return ret; } #endif ret = suspend_nxp_mlc(me->mlcs[0]); if (ret) { PM_DBGOUT("%s: failed to suspend_nxp_mlc0, ret %d\n", __func__, ret); return ret; } ret = suspend_nxp_mlc(me->mlcs[1]); if (ret) { PM_DBGOUT("%s: failed to suspend_nxp_mlc1, ret %d\n", __func__, ret); return ret; } PM_DBGOUT("-%s\n", __func__); return 0; }
int suspend_nxp_resc(struct nxp_resc *me) { PM_DBGOUT("%s\n", __func__); return 0; }
/* Initializes OTG Phy. */ void otg_phy_init(void) { u32 temp; PM_DBGOUT("+%s\n", __func__); writel(readl(SOC_VA_RSTCON + 0x3C) & ~0xF800, SOC_VA_RSTCON + 0x3C); // 1. Release otg common reset writel(readl(SOC_VA_RSTCON + 0x04) & ~(1<<25), SOC_VA_RSTCON + 0x04); // reset on udelay(10); writel(readl(SOC_VA_RSTCON + 0x04) | (1<<25), SOC_VA_RSTCON + 0x04); // reset off udelay(10); // 1-1. VBUS reconfig - Over current Issue #if 1 temp = readl(SOC_VA_TIEOFF + 0x38) & ~(0x7<<23); #if defined(CFG_OTG_OVC_VALUE) temp |= (CFG_OTG_OVC_VALUE << 23); #else temp |= (0x3<<23); #endif writel(temp, SOC_VA_TIEOFF + 0x38); #endif // 2. Program scale mode to real mode writel(readl(SOC_VA_TIEOFF + 0x30) & ~(3<<0), SOC_VA_TIEOFF + 0x30); // 3. Select word interface and enable word interface selection #if 0 writel(readl(SOC_VA_TIEOFF + 0x38) & ~(3<<8), SOC_VA_TIEOFF + 0x38); writel(readl(SOC_VA_TIEOFF + 0x38) | (1<<8), SOC_VA_TIEOFF + 0x38); // 2'b01 8bit, 2'b11 16bit word #else writel(readl(SOC_VA_TIEOFF + 0x38) | (3<<8), SOC_VA_TIEOFF + 0x38); // 2'b01 8bit, 2'b11 16bit word #endif // 4. Select VBUS // writel(readl(SOC_VA_TIEOFF + 0x34) | (3<<24), SOC_VA_TIEOFF + 0x34); /* Select VBUS 3.3V */ writel(readl(SOC_VA_TIEOFF + 0x34) & ~(3<<24), SOC_VA_TIEOFF + 0x34); /* Select VBUS 5V */ // 5. POR of PHY #if 0 writel(readl(SOC_VA_TIEOFF + 0x34) | (3<<7), SOC_VA_TIEOFF + 0x34); #else temp = readl(SOC_VA_TIEOFF + 0x34); temp &= ~(3<<7); temp |= (1<<7); writel(temp, SOC_VA_TIEOFF + 0x34); udelay(1); temp |= (3<<7); writel(temp, SOC_VA_TIEOFF + 0x34); udelay(1); temp &= ~(2<<7); writel(temp, SOC_VA_TIEOFF + 0x34); #endif udelay(10); // 40us delay need. // 6. UTMI reset writel(readl(SOC_VA_TIEOFF + 0x34) | (1<<3), SOC_VA_TIEOFF + 0x34); udelay(1); // 10 clock need // 7. AHB reset writel(readl(SOC_VA_TIEOFF + 0x34) | (1<<2), SOC_VA_TIEOFF + 0x34); udelay(1); // 10 clock need }
int nxp_usb_phy_exit(struct platform_device *pdev, int type) { u32 temp; PM_DBGOUT("++ %s\n", __func__); if (!pdev) return -EINVAL; if( type == NXP_USB_PHY_OTG ) { temp = readl(SOC_VA_TIEOFF + 0x34); // 0. Select VBUS temp |= (3<<24); /* Select VBUS 3.3V */ // temp &= ~(3<<24); /* Select VBUS 5V */ writel(temp, SOC_VA_TIEOFF + 0x34); // 1. UTMI reset temp &= ~(1<<3); writel(temp, SOC_VA_TIEOFF + 0x34); // 2. AHB reset temp &= ~(1<<2); writel(temp, SOC_VA_TIEOFF + 0x34); // 3. POR of PHY #if 0 writel(readl(SOC_VA_TIEOFF + 0x34) | (3<<7), SOC_VA_TIEOFF + 0x34); #else temp = readl(SOC_VA_TIEOFF + 0x34); temp &= ~(3<<7); temp |= (1<<7); writel(temp, SOC_VA_TIEOFF + 0x34); udelay(1); temp |= (3<<7); writel(temp, SOC_VA_TIEOFF + 0x34); udelay(1); temp &= ~(2<<7); writel(temp, SOC_VA_TIEOFF + 0x34); #endif // OTG reset on writel(readl(SOC_VA_RSTCON + 0x04) & ~(1<<25), SOC_VA_RSTCON + 0x04); } else { #if 0 // EHCI, OHCI reset on writel(readl(SOC_VA_RSTCON + 0x04) & ~(1<<24), SOC_VA_RSTCON + 0x04); #else // EHCI, OHCI reset on writel(readl(SOC_VA_RSTCON + 0x04) & ~(1<<24), SOC_VA_RSTCON + 0x04); // 6. Release ahb reset of EHCI, OHCI writel(readl(SOC_VA_TIEOFF + 0x14) & ~(7<<17), SOC_VA_TIEOFF + 0x14); // 5. Release utmi reset writel(readl(SOC_VA_TIEOFF + 0x14) & ~(7<<20), SOC_VA_TIEOFF + 0x14); // 4. POR of PHY #if 0 writel(readl(SOC_VA_TIEOFF + 0x20) | (3<<7), SOC_VA_TIEOFF + 0x20); #else temp = readl(SOC_VA_TIEOFF + 0x20); temp &= ~(3<<7); temp |= (1<<7); writel(temp, SOC_VA_TIEOFF + 0x20); udelay(1); temp |= (3<<7); writel(temp, SOC_VA_TIEOFF + 0x20); udelay(1); temp &= ~(2<<7); writel(temp, SOC_VA_TIEOFF + 0x20); #endif if (type == NXP_USB_PHY_HSIC) { // Clear HSIC mode writel(readl(SOC_VA_TIEOFF + 0x14) & ~(3<<23), SOC_VA_TIEOFF + 0x14); // POR of HSIC PHY writel(readl(SOC_VA_TIEOFF + 0x28) | (3<<18), SOC_VA_TIEOFF + 0x28); } // Wait clock of PHY - about 40 micro seconds udelay(10); // 40us delay need. // EHCI, OHCI reset on // writel(readl(SOC_VA_RSTCON + 0x04) & ~(1<<24), SOC_VA_RSTCON + 0x04); #endif } PM_DBGOUT("-- %s\n", __func__); return 0; }
int nxp_usb_phy_init(struct platform_device *pdev, int type) { PM_DBGOUT("++ %s\n", __func__); if (!pdev) return -EINVAL; if( type == NXP_USB_PHY_OTG ) { u32 temp; // 1. Release otg common reset writel(readl(SOC_VA_RSTCON + 0x04) & ~(1<<25), SOC_VA_RSTCON + 0x04); // reset on udelay(1); writel(readl(SOC_VA_RSTCON + 0x04) | (1<<25), SOC_VA_RSTCON + 0x04); // reset off // 2. Program scale mode to real mode writel(readl(SOC_VA_TIEOFF + 0x30) & ~(3<<0), SOC_VA_TIEOFF + 0x30); // 3. Select word interface and enable word interface selection #if (HOST_SS_BUS_WIDTH16 == 1) writel(readl(SOC_VA_TIEOFF + 0x38) | (3<<8), SOC_VA_TIEOFF + 0x38); // 2'b01 8bit, 2'b11 16bit word #else writel(readl(SOC_VA_TIEOFF + 0x38) & ~(3<<8), SOC_VA_TIEOFF + 0x38); #endif // 4. Select VBUS temp = readl(SOC_VA_TIEOFF + 0x34); temp &= ~(3<<24); /* Analog 5V */ // temp |= (3<<24); /* Digital 3.3V */ writel(temp, SOC_VA_TIEOFF + 0x34); // 5. POR of PHY temp &= ~(3<<7); temp |= (1<<7); writel(temp, SOC_VA_TIEOFF + 0x34); #if 1 udelay(1); writel(readl(SOC_VA_TIEOFF + 0x34) | (3<<7), SOC_VA_TIEOFF + 0x34); #endif udelay(10); // 40us delay need. // 6. UTMI reset temp |= (1<<3); writel(temp, SOC_VA_TIEOFF + 0x34); udelay(1); // 10 clock need // 7. AHB reset temp |= (1<<2); writel(temp, SOC_VA_TIEOFF + 0x34); udelay(1); // 10 clock need } else { u32 fladj_val, bit_num, bit_pos = 21; // fladj_val0 u32 temp1, temp2, temp3; // 0. Set FLADJ Register. fladj_val = 0x20; #if 0 temp1 = readl(SOC_VA_TIEOFF + 0x1C) & ~(0x1FFFFFF); temp2 = temp1 | fladj_val; #else temp2 = fladj_val; #endif for (bit_num = 0; bit_num < 6; bit_num++) { if (fladj_val & (1<<bit_num)) temp2 |= (0x7 << bit_pos); bit_pos -= 3; } writel(temp2, SOC_VA_TIEOFF + 0x1C); // 1. Release common reset of host controller writel(readl(SOC_VA_RSTCON + 0x04) & ~(1<<24), SOC_VA_RSTCON + 0x04); // reset on udelay(1); if (type == NXP_USB_PHY_HSIC) { #if defined (CFG_GPIO_HSIC_EXTHUB_RESET) // GPIO Reset nxp_soc_gpio_set_io_dir(CFG_GPIO_HSIC_EXTHUB_RESET, CTRUE); nxp_soc_gpio_set_io_pull_enb(CFG_GPIO_HSIC_EXTHUB_RESET, CTRUE); nxp_soc_gpio_set_out_value(CFG_GPIO_HSIC_EXTHUB_RESET, CTRUE); udelay( 10 ); nxp_soc_gpio_set_out_value(CFG_GPIO_HSIC_EXTHUB_RESET, CFALSE); udelay( 10 ); nxp_soc_gpio_set_out_value(CFG_GPIO_HSIC_EXTHUB_RESET, CTRUE); #else printk("is there extern hub on hsic port???\n"); #endif } writel(readl(SOC_VA_RSTCON + 0x04) | (1<<24), SOC_VA_RSTCON + 0x04); // reset off if (type == NXP_USB_PHY_HSIC) { // HSIC 12M rerference Clock setting writel( 0x02, USB2_HOST_CLKGEN); writel( 0x0C, USB2_HOST_CLKGEN + 0x4); // 8 : ok, c : no writel( 0x10, USB2_HOST_CLKGEN + 0xc); writel( 0x30, USB2_HOST_CLKGEN + 0xc); writel( 0x06, USB2_HOST_CLKGEN); // HSIC 480M clock setting writel(readl(SOC_VA_TIEOFF + 0x14) & ~(3<<23), SOC_VA_TIEOFF + 0x14); writel(readl(SOC_VA_TIEOFF + 0x14) | (2<<23), SOC_VA_TIEOFF + 0x14); // HSIC Enable in PORT1 of LINK writel(readl(SOC_VA_TIEOFF + 0x14) & ~(7<<14), SOC_VA_TIEOFF + 0x14); writel(readl(SOC_VA_TIEOFF + 0x14) | (2<<14), SOC_VA_TIEOFF + 0x14); } // 2. Program AHB Burst type temp1 = readl(SOC_VA_TIEOFF + 0x1C) & ~HOST_SS_DMA_BURST_MASK; if (type == NXP_USB_PHY_OHCI) writel(temp1 | OHCI_SS_ENABLE_DMA_BURST, SOC_VA_TIEOFF + 0x1C); else writel(temp1 | EHCI_SS_ENABLE_DMA_BURST, SOC_VA_TIEOFF + 0x1C); // 3. Select word interface and enable word interface selection temp1 = readl(SOC_VA_TIEOFF + 0x14) | (3<<25); // 2'b01 8bit, 2'b11 16bit word temp2 = readl(SOC_VA_TIEOFF + 0x24) | (3<<8); // 2'b01 8bit, 2'b11 16bit word temp3 = readl(SOC_VA_TIEOFF + 0x2C) | (3<<12); // 2'b01 8bit, 2'b11 16bit word #if (HOST_SS_BUS_WIDTH16 == 0) temp1 &= ~(2<<25); temp2 &= ~(2<<8); temp3 &= ~(2<<12); #endif writel(temp1, SOC_VA_TIEOFF + 0x14); writel(temp2, SOC_VA_TIEOFF + 0x24); if (type == NXP_USB_PHY_HSIC) writel(temp3, SOC_VA_TIEOFF + 0x2C); // 4. POR of PHY temp1 = readl(SOC_VA_TIEOFF + 0x20); temp1 &= ~(3<<7); temp1 |= (1<<7); writel(temp1, SOC_VA_TIEOFF + 0x20); udelay(10); // 40us delay need. if (type == NXP_USB_PHY_HSIC) { // Set HSIC mode writel(readl(SOC_VA_TIEOFF + 0x14) | (3<<23), SOC_VA_TIEOFF + 0x14); // POR of HSIC PHY writel(readl(SOC_VA_TIEOFF + 0x28) & ~(3<<18), SOC_VA_TIEOFF + 0x28); writel(readl(SOC_VA_TIEOFF + 0x28) | (1<<18), SOC_VA_TIEOFF + 0x28); // Wait clock of PHY - about 40 micro seconds udelay(100); // 40us delay need. } // 5. Release utmi reset temp1 = readl(SOC_VA_TIEOFF + 0x14) | (7<<20); if (type == NXP_USB_PHY_HSIC) writel(temp1, SOC_VA_TIEOFF + 0x14); else writel(temp1 & ~(4<<20), SOC_VA_TIEOFF + 0x14); //6. Release ahb reset of EHCI, OHCI //writel(readl(SOC_VA_TIEOFF + 0x14) & ~(7<<17), SOC_VA_TIEOFF + 0x14); writel(readl(SOC_VA_TIEOFF + 0x14) | (7<<17), SOC_VA_TIEOFF + 0x14); } PM_DBGOUT("-- %s\n", __func__); return 0; }
/* * snd_soc_dai_driver */ static int nxp_spdif_dai_suspend(struct snd_soc_dai *dai) { PM_DBGOUT("%s\n", __func__); return 0; }
int resume_nxp_resc(struct nxp_resc *me) { PM_DBGOUT("%s\n", __func__); return 0; }
static int lcd_suspend(struct disp_process_dev *pdev) { PM_DBGOUT("%s\n", __func__); return lcd_enable(pdev, 0); }
static void lcd_resume(struct disp_process_dev *pdev) { PM_DBGOUT("%s\n", __func__); lcd_enable(pdev, 1); }