Example #1
0
void  ADC_Init (void)
{
	//!!!!!!!! PORTB BIT_2 --> GP2_6 ne fonctionne pas !!!!!!!!!! CBE 29/04/2010
	//Disable all comparators
	DisableCN2;
	DisableCN4;
	DisableCN6;
	DisableCN8;
	DisableCN10;
	DisableCN11;
	PORTSetPinsAnalogIn(IOPORT_B, BIT_2 | BIT_4 | BIT_6 | BIT_8 | BIT_10 | BIT_11);	// Set AN pin as analog input.
	CloseADC10();														// ensure the ADC is off before setting the configuration
    ADC_Config();                                                       /* Configure ADC settings                           */
    EnableADC10();                                                      /* Enable the ADC                                   */
}
Example #2
0
		virtual void setup_analog_in()		{
			CloseADC10(); // ERROR: Only open 2 channels?
			SetChanADC10(ADC_CH0_NEG_SAMPLEA_NVREF|ADC_CH0_POS_SAMPLEA_AN0);

			PORTSetPinsAnalogIn(ltr(), num());

			enabled_ADCs |= (typeof(enabled_ADCs)) (1 << bit); // PIC32 SPECIFIC
			uint32_t count_enabled = __builtin_popcount(enabled_ADCs); // 32bit cuz we bitshift below

			/* 1: Turn module on | ouput in integer | trigger mode auto | enable autosample
			 * 2: ADC ref external    | disable offset test    | disable scan mode | perform 2 samples | use dual buffers | use alternate mode
			 * 3: use ADC internal clock | set sample time
			 * 4: enable all ANX not in use
			 * 5: do not assign other channels to scan */
			#define PARAM1	ADC_MODULE_ON | ADC_FORMAT_INTG | ADC_CLK_AUTO | ADC_AUTO_SAMPLING_ON
			#define PARAM2	ADC_VREF_AVDD_AVSS | ADC_OFFSET_CAL_DISABLE | ADC_SCAN_ON | (count_enabled << _AD1CON2_SMPI_POSITION) | ADC_ALT_BUF_OFF | ADC_ALT_INPUT_OFF // use Channel A only
			#define PARAM3	ADC_CONV_CLK_INTERNAL_RC | ADC_SAMPLE_TIME_15
			#define PARAM4	ENABLE_AN0_ANA | ENABLE_AN1_ANA
			#define PARAM5	SKIP_SCAN_ALL

			OpenADC10( PARAM1, PARAM2, PARAM3, enabled_ADCs, ~enabled_ADCs ); // setup ADC
			EnableADC10();
		}
void hardwareInit(void)
{
        // Configure the device for maximum performance, but do not change the PBDIV clock divisor.
        // Given the options, this function will change the program Flash wait states,
        // RAM wait state and enable prefetch cache, but will not change the PBDIV.
        // The PBDIV value is already set via the pragma FPBDIV option above.
    SYSTEMConfig(SYS_FREQ, SYS_CFG_WAIT_STATES | SYS_CFG_PCACHE);

    PORTSetPinsAnalogIn(IOPORT_A, BIT_1 | BIT_0);
        // Could also use mPORTDSetPinsDigitalOut(BIT_6 | BIT_7);
    //PORTSetPinsDigitalOut(IOPORT_A, BIT_3 | BIT_2);
    PORTSetPinsDigitalOut(IOPORT_A, BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 );

    PORTSetPinsAnalogIn(IOPORT_B, BIT_2 | BIT_1 | BIT_0);
    PORTSetPinsDigitalOut(IOPORT_B, BIT_15 | BIT_14 | BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_9 | BIT_7 | BIT_4 | BIT_3);
    PORTSetPinsDigitalIn(IOPORT_B, BIT_8 | BIT_6 | BIT_5);

    PORTSetPinsDigitalOut(IOPORT_C, BIT_9 | BIT_7 | BIT_6 | BIT_3 | BIT_2 |BIT_1 | BIT_0);
    PORTSetPinsDigitalIn(IOPORT_C, BIT_8 | BIT_5 | BIT_4);

        // This is the waggle to set reprogrammable peripheral
        // Assume ints & DMA disa
    SYSKEY = 0xAA996655;
    SYSKEY = 0x556699AA;
    U1RXR = 0b0001;     // U2.15 RPB6 as RxD1 (PICO) input
    RPB7R = 0b0001;     // U2.16 RPB7 as TxD1 (POCI) output
    SDI1R = 0b0011;     // U2.22 RPB11 is SDI1
    RPB8R = 0b0011;     // U2.17 RPB8 is SDO1
    SYSKEY = 0x33333333;    // Junk relocks it

    OSCCONbits.SOSCEN = 1;
    OSCCONbits.SOSCRDY = 1;
        // Serial port on UART1
        // Note, Mode & Sta have atomic bit clr, set, & inv registers
    U1MODEbits.ON = 1;      // Ena UART1, per UEN, with UTXEN
    U1MODEbits.SIDL = 0;    // Continue oper in idle mode
    U1MODEbits.IREN = 0;    // Disa IrDA
    U1MODEbits.RTSMD = 1;   // U1RTS_n pin in simplex mode
    U1MODEbits.UEN = 0b00;  // U1CTS_n & U1RTS_n unused
    U1MODEbits.WAKE = 0;    // Disa wakeup
    U1MODEbits.LPBACK = 0;  // Disa loopback
    U1MODEbits.ABAUD = 0;   // Disa autobaud
    U1MODEbits.RXINV = 0;   // U1Rx 0 for idle high
    U1MODEbits.BRGH = 0;    // Std speed 16x, 1: high speed is 4x baud clk
    U1MODEbits.PDSEL = 0b00;    // 8 bit data, no parity
    U1MODEbits.STSEL = 0;   // 1 stop bit

    U1STAbits.ADM_EN = 0;   // Disa automatic address mode detect
    U1STAbits.UTXISEL = 0b01;   // Interrupt gen when all chars transmitted
    U1STAbits.UTXINV = 0;  // U1Tx idle is 1.
    U1STAbits.URXEN = 1;    // Ena U1Rx
    U1STAbits.UTXBRK = 0;   // Disa Break (Start bit, then 12 0's, Stop)
    U1STAbits.UTXEN = 1;    // Ena U1Tx
    U1STAbits.URXISEL = 0b01;   // Interrupt flag asserted while buffer is 1/2 or more full
    U1STAbits.ADDEN = 0;    // Disa address mode

    U1BRG = 162;            // 80 for 19200 baud = PBCLK / (16 x (BRG + 1)), PBCLK = 25 MHz @ div / 1, Jitter 0.47%
                            // 162 for 9600, 325 for 4800

    RS485_DE = 0;
    RS485_RE_n = 0;

    AD1CON1bits.FORM = 0b000;   // Integer 16-bit, 10 lsb's
    AD1CON1bits.SSRC = 0b111;   // Internal ctr ends sampling and starte conver, auto.
    AD1CON1bits.ASAM = 1;       // Sampling begins immediately after last conversion completes; SAMP bit is automatically set
    AD1CON1bits.SAMP = 1;       // Ena sampling

    AD1CON2bits.VCFG = 0b001;   // Vref+ has bandgap ref, use Vss
    AD1CON2bits.OFFCAL = 0;     // Disa offset cal mode
    AD1CON2bits.CSCNA = 0;      // Disa scan the inputs
    AD1CON2bits.BUFM = 0;       // Buffer is one 16-bit word
    AD1CON2bits.ALTS = 0;       // Always use sample A input mux settings

    AD1CON3bits.ADRC = 1;       // ADC clk from FRC
    AD1CON3bits.SAMC = 0b11111; // 31 x TAD autosample time
    AD1CON3bits.ADCS = 0xFF;    // 512 x TPB = TAD, TPB from PBCLK

        // These don't matter if we scan.
    AD1CHSbits.CH0NB = 0;       // Sample B Ch 0 neg input is Vrefl
    AD1CHSbits.CH0SB = 0b00000; // Select B: AN0
    AD1CHSbits.CH0NA = 0;       // Sample A Ch 0 neg input is Vrefl
    AD1CHSbits.CH0SA = 0b00000; // Select B: AN0

    AD1CON1bits.ON = 1;         // This must be last step.

//    SPI1CONbits.MSTEN = 1;      // Master mode.  Shd be first command.
//    SPI1CONbits.FRMEN = 0;      // Framed SPI disa
//    SPI1CONbits.MSSEN = 0;      // Slave select SPI support disa
//    SPI1CONbits.MCLKSEL = 0;    // Use PBCLK for BRG
//    SPI1CONbits.ENHBUF = 0;     // Enhanced buffer disa
//    SPI1CONbits.ON = 0;         // Turn it off for now
//    SPI1CONbits.SIDL = 0;       // Continue in Idle
//    SPI1CONbits.DISSDO = 0;     // Use SDOx
//    SPI1CONbits.MODE16 = 0;     // 8 bit transfer
//    SPI1CONbits.MODE32 = 0;     // 8 bit transfer
//    SPI1CONbits.SMP = 0;        // Sample data in middle of phase
//    SPI1CONbits.CKE = 0;        // Serial output data changes on transition from idle clock state to active clock state
//    SPI1CONbits.SSEN = 0;       // Do not use /SS1 pin
//    SPI1CONbits.CKP = 0;        // Idle clock is low
//
//    SPI1CONbits.DISSDI = 0;     // Use SDI1 pin
//
//    SPI1CON2bits.AUDEN = 0;     // Audio protocol disa
//    SPI1BRG = 0x100;

   // spiIoxConfig();

    LED_GREEN = 0;
}