Example #1
0
int PSCModuleControl (unsigned int baseAdd, unsigned int moduleId,
                         unsigned int powerDomain, unsigned int flags)
{
    volatile unsigned int timeout = 0xFFFFFF;
    int    retVal = 0;
    unsigned int    status = 0;

    HWREG(baseAdd +  PSC_MDCTL(moduleId)) = (flags & PSC_MDCTL_NEXT);

    if (powerDomain == 0)
    {
        HWREG(baseAdd + PSC_PTCMD) = PSC_PTCMD_GO0;
    }
    else
    {
        HWREG(baseAdd + PSC_PTCMD) = PSC_PTCMD_GO1;
    }

    if (powerDomain == 0)
    {
        do {
            status = HWREG(baseAdd + PSC_PTSTAT) & PSC_PTSTAT_GOSTAT0;
        } while (status && timeout--);
    }
    else
    {
        do {
            status = HWREG(baseAdd + PSC_PTSTAT) & PSC_PTSTAT_GOSTAT1;
        } while (status && timeout--);
    }

    if (timeout != 0)
    {
        timeout = 0xFFFFFF;
        status = flags & PSC_MDCTL_NEXT; 
        do {
            timeout--;
        } while(timeout && 
                (HWREG(baseAdd + PSC_MDSTAT(moduleId)) & PSC_MDSTAT_STATE) != status);
    }

    if (timeout == 0)
    {
        retVal = -1;
    }

    return retVal;
}
int PSCModuleControl(unsigned int baseAdd, unsigned int moduleId,
                     unsigned int powerDomain, unsigned int flags)
{
	/*
		PSC???
	
		managing transitions of system power on/off,
		clock on/off, resets (device level and module level).
		
		 primarily to provide granular power control
		for on chip modules (peripherals and CPU).
	*/
	
	/*
		baseAdd			0x01E27000
		 -> PSC1 BYTE ADDRESS(0x01E2 7000) 
		  -> REVID(Peripheral Revision and Class Information Register)
		moduleId 		3
		powerDomain		0
		flags			0x00000003u
	*/

    volatile unsigned int timeout = 0xFFFFFF;
    int retVal = 0;
    unsigned int status = 0;

    HWREG(baseAdd +  PSC_MDCTL(moduleId)) = (flags & PSC_MDCTL_NEXT);
	/*
		#define HWREG(x)	(*((volatile unsigned int *)(x)))

		baseAdd = 0x01E27000

		PSC_MDCTL(moduleId)
		#define PSC_MDCTL(n)	(0xA00 + (n * 4))
		moduleId = 3 -> 0xA0C

		baseAdd + PSC_MDCTL(moduleId) -> 0x01E2 7A0C
		-> 0x01E2 7A0C -> MDCTL3 -> Module 3 Control Register

		(flags & PSC_MDCTL_NEXT)
		flags = 0x00000003u, PSC_MDCTL_NEXT = 0x0000 001Fu -> & -> 0x3

		MDCTL3 = 0x3
		 -> PSC1 Module Control 3 Register -> Enable state
		  -> GPIO( alwaysON(PD0) )
	*/

    if (powerDomain == 0) //powerDomain = 0 
	{
	/*
		POWER DOMAIN???
		
		• ON: power to the domain is on
		• OFF: power to the domain is off
		
		the Always ON domain (or PD0 power domain)
		
		Additionally, for both PSC0 and PSC1, the PD1 power domains,
		the internal/pseudo power domain can either be in the ON state or OFF state.		
	*/
	
        HWREG(baseAdd + PSC_PTCMD) = PSC_PTCMD_GO0;
		/*
			baseAdd = 0x01E27000
			
			PSC_PTCMD = 0x120
			
			+ -> 0x1E27120 -> HWREG(0x1E27120) 
			   -> *((volatile unsigned int *)(0x1E27120))
			    -> PTCMD(Power Domain Transition Command Register)
			
			#define PSC_PTCMD_GO0          (0x00000001u)
			
			PTCMD = 0x0000 0001u
			 -> Always ON (PD0) power domain GO transition command.
		*/
    }
    else //powerDomain != 0	
    {
        HWREG(baseAdd + PSC_PTCMD) = PSC_PTCMD_GO1;
		/*
			#define PSC_PTCMD_GO1          (0x00000002u)
			
			PTCMD = 0x00000002u
			-> RAM/Pseudo (PD1) power domain GO transition command.		
		*/
    }

    if (powerDomain == 0) //powerDomain = 0
    {
        do {
            status = HWREG(baseAdd + PSC_PTSTAT) & PSC_PTSTAT_GOSTAT0;
			/*
				baseAdd = 0x01E27000
				 PSC_PTSTAT = 0x128 
				  [+] -> 0x1E2 7128
					HWREG(0x1E2 7128)
					 -> PTSTAT(Power Domain Transition Status Register)
				
				PSC_PTSTAT_GOSTAT0 = 0x0000 0001u
				 & -> only GOSTAT[0] is 1
				  -> Always ON (PD0) power domain transition status.
				   -> status
			*/
	    
        } while (status && timeout--);
		/*
			status && timeout(= 0xFFFFFF)
		*/
    }
    else //powerDomain != 0
    {
        do {
            status = HWREG(baseAdd + PSC_PTSTAT) & PSC_PTSTAT_GOSTAT1;
			/*
				HWREG(baseAdd + PSC_PTSTAT) -> PTSTAT 
				 #define PSC_PTSTAT_GOSTAT1     (0x00000002u)
				  & -> only GOSTAT[1] is 1
				   -> RAM/Pseudo (PD1) power domain transition status.
				   -> status
			*/
        } while (status && timeout--);
		/*
			status && timeout(= 0xFFFFFF)
		*/
    }

    if(timeout != 0)
    {
        timeout = 0xFFFFFF;

        status = flags & PSC_MDCTL_NEXT; 
		/*
			flags = 0x0000 0003u
			
			PSC_MDCTL_NEXT = 0x0000 001Fu
			
			& -> 0x0000 0003u -> status
		*/

        do {
            timeout--;
			//timeout = 0xFFFFFE

        } while(timeout && 
                (HWREG(baseAdd + PSC_MDSTAT(moduleId)) & PSC_MDSTAT_STATE) != status);
			/*
				timeout = 0xFFFFFE
				
				baseAdd = 0x01E27000
				 
				#define PSC_MDSTAT(n)	(0x800 + (n * 4))
				 moduleId = 3 -> PSC_MDSTAT(moduleId) -> 0x80C
				
				HWREG(baseAdd + PSC_MDSTAT(moduleId) -> 
				HWREG( 0x01E2 780C ) -> MDSTAT3(Module 3 Status Register)
				
				PSC_MDSTAT_STATE = 0x0000 0003Fu
				
				while( timeout && ( MDSTAT3 & PSC_MDSTAT_STATE ) != status )
			*/
    }

    if (timeout == 0)//if fail, return -1
    {
        retVal = -1; 
    }

    return retVal;
}