INLINE void STORE_REGFILE(offs_t addr, UINT8 data) /* Write to internal memory */
{
if ((picmodel == 0x16C57) || (picmodel == 0x16C58))
{
addr |= (R.FSR & 0x60);
}
if ((addr & 0x10) == 0) addr &= 0x0f;
switch(addr)
{
case 00: addr = (R.FSR & picRAMmask);
if (addr == 0) break;
if ((addr & 0x10) == 0) addr &= 0x0f;
R.picRAM[addr] = data; break; /* Indirect address */
case 01: delay_timer = 2; /* Timer starts after next two instructions */
if (PSA == 0) R.prescaler = 0; /* Must clear the Prescaler */
R.TMR0 = data; break;
case 02: R.PCL = data;
R.PC = ((R.STATUS & PA_REG) << 4) | data; break;
case 03: R.STATUS &= ~PA_REG; R.STATUS |= (data & PA_REG); break;
case 04: R.FSR = (data | (~picRAMmask)); break;
case 05: data &= 0xf; /* 4-bit port (only lower 4 bits used) */
P_OUT(0,data & (~R.TRISA)); R.PORTA = data; break;
case 06: P_OUT(1,data & (~R.TRISB)); R.PORTB = data; break;
case 07: if ((picmodel == 0x16C55) || (picmodel == 0x16C57)) {
P_OUT(2,data & (~R.TRISC));
R.PORTC = data;
}
else { /* PIC16C54, PIC16C56, PIC16C58 */
R.picRAM[addr] = data;
}
break;
default: R.picRAM[addr] = data; break;
}
}
static void tris(void)
{
switch(R.opcode.b.l & 0x7)
{
case 05: if (R.TRISA == R.W) break;
else R.TRISA = R.W; P_OUT(0,R.PORTA & (~R.TRISA) & 0xf); break;
case 06: if (R.TRISB == R.W) break;
else R.TRISB = R.W; P_OUT(1,R.PORTB & (~R.TRISB)); break;
case 07: if (R.TRISC == R.W) break;
else R.TRISC = R.W; P_OUT(2,R.PORTC & (~R.TRISC)); break;
default: illegal(); break;
}
}
void pic16c62x_device::STORE_REGFILE(offs_t addr, UINT8 data) /* Write to internal memory */
{
if (addr == 0) { /* Indirect addressing */
addr = (FSR & m_picRAMmask);
}
switch(addr)
{
case 0x80:
case 0x00: /* Not an actual register, nothing to save */
break;
case 0x01: m_delay_timer = 2; /* Timer starts after next two instructions */
if (PSA == 0) m_prescaler = 0; /* Must clear the Prescaler */
TMR0 = data;
break;
case 0x82:
case 0x02: PCL = data;
m_PC = (m_PCLATH << 8) | data;
break;
case 0x83:
case 0x03: STATUS &= (UINT8)(~(IRP_FLAG|RP1_FLAG|RP0_FLAG)); STATUS |= (data & (IRP_FLAG|RP1_FLAG|RP0_FLAG));
break;
case 0x84:
case 0x04: FSR = (data | (UINT8)(~m_picRAMmask));
break;
case 0x05: data &= 0x1f; /* 5-bit port (only lower 5 bits used) */
P_OUT(0,data & (UINT8)(~m_TRISA)); PORTA = data;
break;
case 0x06: P_OUT(1,data & (UINT8)(~m_TRISB)); PORTB = data;
break;
case 0x8a:
case 0x0a:
m_PCLATH = data & 0x1f;
M_WRTRAM(0x0a, m_PCLATH);
break;
case 0x8b:
case 0x0b: M_WRTRAM(0x0b, data);
break;
case 0x81: m_OPTION = data;
M_WRTRAM(0x81, data);
break;
case 0x85: if (m_TRISA != data)
{
m_TRISA = data | 0xf0;
P_OUT(2,m_TRISA);
P_OUT(0,PORTA & (UINT8)(~m_TRISA) & 0x0f);
M_WRTRAM(addr, data);
}
break;
case 0x86: if (m_TRISB != data)
{
m_TRISB = data;
P_OUT(3,m_TRISB);
P_OUT(1,PORTB & (UINT8)(~m_TRISB));
M_WRTRAM(addr, data);
}
break;
default: M_WRTRAM(addr, data);
break;
}
}
