VOID
STATIC
PcieSiliconEnablePortsV5 (
IN PCIe_SILICON_CONFIG *Silicon,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_ENGINE_CONFIG *EngineList;
EngineList = PcieConfigGetChildEngine (Silicon);
while (EngineList != NULL) {
if (PcieConfigIsPcieEngine (EngineList)) {
if (!PcieConfigIsSbPcieEngine (EngineList) &&
(PcieConfigCheckPortStatus (EngineList, INIT_STATUS_PCIE_TRAINING_SUCCESS) ||
((EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) &&
(EngineList->Type.Port.PortData.LinkHotplug != HotplugInboard)))) {
GnbLibPciIndirectRMW (
Silicon->Address.AddressValue | D0F0xC8_ADDRESS,
D0F0xCC_x01_ADDRESS | ((EngineList->Type.Port.PortData.DeviceNumber << 3 | EngineList->Type.Port.PortData.FunctionNumber) << D0F0xC8_NB_DEV_IND_SEL_OFFSET),
AccessS3SaveWidth32,
(UINT32)~(D0F0xCC_x01_BridgeDis_MASK | D0F0xCC_x01_CfgDis_MASK | D0F0xCC_x01_CsrEnable_MASK | D0F0xCC_x01_SetPowEn_MASK),
((1 << D0F0xCC_x01_CsrEnable_OFFSET) | (1 << D0F0xCC_x01_SetPowEn_OFFSET)),
GnbLibGetHeader (Pcie)
);
}
}
EngineList = (PCIe_ENGINE_CONFIG *) PcieConfigGetNextTopologyDescriptor (EngineList, DESCRIPTOR_TERMINATE_GNB);
}
}
VOID
STATIC
PcieUtilGlobalGenCapabilityCallback (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIE_GLOBAL_GEN_CAP_WORKSPACE *GlobalGenCapability;
PCIE_LINK_SPEED_CAP LinkSpeedCapability;
PCIE_HOTPLUG_TYPE HotPlugType;
UINT32 Flags;
Flags = PCIE_GLOBAL_GEN_CAP_ALL_PORTS;
GlobalGenCapability = (PCIE_GLOBAL_GEN_CAP_WORKSPACE*) Buffer;
LinkSpeedCapability = PcieGen1;
if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
Flags |= PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS;
}
HotPlugType = Engine->Type.Port.PortData.LinkHotplug;
if ((HotPlugType == HotplugBasic) || (HotPlugType == HotplugServer) || (HotPlugType == HotplugEnhanced)) {
Flags |= PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS;
}
if ((GlobalGenCapability->Flags & Flags) != 0) {
ASSERT ((GlobalGenCapability->Flags & (PCIE_PORT_GEN_CAP_MAX | PCIE_PORT_GEN_CAP_BOOT)) != 0);
LinkSpeedCapability = PcieFmGetLinkSpeedCap (GlobalGenCapability->Flags, Engine, Pcie);
if (GlobalGenCapability->LinkSpeedCapability < LinkSpeedCapability) {
GlobalGenCapability->LinkSpeedCapability = LinkSpeedCapability;
}
}
}
VOID
STATIC
PciePortPostS3InitCallback (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIE_LINK_SPEED_CAP LinkSpeedCapability;
ASSERT (Engine->EngineData.EngineType == PciePortEngine);
LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine, Pcie);
PcieSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie);
if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) {
PcieLinkSafeMode (Engine, Pcie);
}
if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) {
PcieForceCompliance (Engine, Pcie);
}
if (!Engine->Type.Port.IsSB) {
if ((PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) ||
((Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) && (Engine->Type.Port.PortData.LinkHotplug != HotplugInboard)) ||
(Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1))) {
PcieTrainingSetPortState (Engine, LinkStateResetExit, FALSE, Pcie);
} else {
PcieTrainingSetPortState (Engine, LinkStateDeviceNotPresent, FALSE, Pcie);
}
PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS);
} else {
PcieTrainingSetPortState (Engine, LinkStateTrainingSuccess, FALSE, Pcie);
}
}
VOID
STATIC
PciePortPostInitCallback (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIE_LINK_SPEED_CAP LinkSpeedCapability;
ASSERT (Engine->EngineData.EngineType == PciePortEngine);
if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) {
PcieLinkSafeMode (Engine, Pcie);
}
LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine, Pcie);
PcieSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie);
// Retrain only present port to Gen2
if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) && (LinkSpeedCapability > PcieGen1) && !Engine->Type.Port.IsSB) {
PcieTrainingSetPortState (Engine, LinkStateRetrain, FALSE, Pcie);
PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS);
}
// Train ports forced to compliance
if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) {
PcieForceCompliance (Engine, Pcie);
PcieTrainingSetPortState (Engine, LinkStateResetExit, FALSE, Pcie);
}
}
VOID
STATIC
PciePostS3PortInitCallbackML (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIE_LINK_SPEED_CAP LinkSpeedCapability;
PCIE_LINK_TRAINING_STATE State;
ASSERT (Engine->EngineData.EngineType == PciePortEngine);
LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine);
PcieSetLinkSpeedCapV4 (LinkSpeedCapability, Engine, Pcie);
if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) {
PcieLinkSafeMode (Engine, Pcie);
}
if (!PcieConfigIsSbPcieEngine (Engine)) {
//
// General Port
//
State = LinkStateDeviceNotPresent;
if (Engine->Type.Port.PortData.LinkHotplug == HotplugDisabled || Engine->Type.Port.PortData.LinkHotplug == HotplugInboard) {
//
// Non hotplug device: we only check status from previous boot
//
if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
State = LinkStateResetExit;
}
} else {
UINT32 PcieScratch;
//
// Get endpoint staus from scratch
//
PcieScratch = PciePortRegisterRead (Engine, DxFxxE4_x01_ADDRESS, Pcie);
//
// Hotplug device: we check ep status if reported
//
if ((PcieScratch & 0x1) == 0) {
State = LinkStateResetExit;
}
}
//
// For compliance we always leave link in enabled state
//
if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode) {
State = LinkStateResetExit;
}
PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS);
} else {
//
// SB port
//
State = LinkStateTrainingSuccess;
}
PcieTrainingSetPortStateV2 (Engine, State, FALSE, Pcie);
}
VOID
STATIC
PcieAlibSetPortOverrideSpeedCallback (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 *PsppOverridePortSpeedPackage;
PsppOverridePortSpeedPackage = (UINT8*) Buffer;
if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
PsppOverridePortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = Engine->Type.Port.PortData.MiscControls.LinkSafeMode;
}
if (Engine->Type.Port.PortData.LinkHotplug == HotplugBasic && !PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
PsppOverridePortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = PcieGen1;
}
}
VOID
STATIC
PcieAlibSetPortMaxSpeedCallback (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT8 *PsppMaxPortSpeedPackage;
PsppMaxPortSpeedPackage = (UINT8*) Buffer;
if (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
PsppMaxPortSpeedPackage[(Engine->Type.Port.Address.Address.Device - 2) * 2 + 1] = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine, Pcie);
}
}
/**
* Check is engine is active or potentially active
*
*
*
* @param[in] Engine Pointer to engine descriptor
* @retval TRUE - engine active
* @retval FALSE - engine not active
*/
BOOLEAN
PcieConfigIsActivePcieEngine (
IN PCIe_ENGINE_CONFIG *Engine
)
{
BOOLEAN Result;
ASSERT (PcieConfigIsPcieEngine (Engine));
Result = FALSE;
if (PcieConfigIsEngineAllocated (Engine)) {
if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) ||
(Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled && Engine->Type.Port.PortData.LinkHotplug != HotplugInboard)) {
Result = TRUE;
}
}
return Result;
}
VOID
STATIC
PcieClkPmPortInitCallback (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
if (Engine->Type.Port.PortData.MiscControls.ClkPmSupport == 0x1 &&
!PcieConfigIsSbPcieEngine (Engine) &&
PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
PcieClkPmPortInitConfigure (
Engine->Type.Port.Address,
GnbLibGetHeader (Pcie)
);
}
}
VOID
STATIC
PcieAspmPortInitCallback (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
if (Engine->Type.Port.PortData.LinkAspm != AspmDisabled &&
!PcieConfigIsSbPcieEngine (Engine) &&
PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
excel950_fun2 (
Engine->Type.Port.Address,
Engine->Type.Port.PortData.LinkAspm,
GnbLibGetHeader (Pcie)
);
}
}
VOID
PcieSiliconHidePorts (
IN PCIe_SILICON_CONFIG *Silicon,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
D0F0x64_x0C_STRUCT D0F0x64_x0C;
PCIe_WRAPPER_CONFIG *WrapperList;
D0F0x64_x0C.Value = 0;
WrapperList = PcieSiliconGetWrapperList (Silicon);
while (WrapperList != NULL) {
PCIe_ENGINE_CONFIG *EngineList;
EngineList = PcieWrapperGetEngineList (WrapperList);
while (EngineList != NULL) {
if (EngineList->EngineData.EngineType == PciePortEngine) {
if (!PcieConfigCheckPortStatus (EngineList, INIT_STATUS_PCIE_TRAINING_SUCCESS) &&
((EngineList->Type.Port.PortData.LinkHotplug == HotplugDisabled) || (EngineList->Type.Port.PortData.LinkHotplug == HotplugInboard)) &&
!EngineList->Type.Port.IsSB) {
D0F0x64_x0C.Value |= 1 << EngineList->Type.Port.NativeDevNumber;
}
}
EngineList = PcieLibGetNextDescriptor (EngineList);
}
WrapperList = PcieLibGetNextDescriptor (WrapperList);
}
GnbLibPciIndirectRMW (
Silicon->Address.AddressValue | D0F0x60_ADDRESS,
D0F0x64_x0C_ADDRESS | IOC_WRITE_ENABLE,
AccessS3SaveWidth32,
~(UINT32)(BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7),
D0F0x64_x0C.Value,
GnbLibGetHeader (Pcie)
);
GnbLibPciIndirectRMW (
Silicon->Address.AddressValue | D0F0x60_ADDRESS,
D0F0x64_x00_ADDRESS | IOC_WRITE_ENABLE,
AccessS3SaveWidth32,
~(UINT32)BIT6,
0x0,
GnbLibGetHeader (Pcie)
);
}
VOID
STATIC
PcieCommClkCfgPortInitCallback (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCI_ADDR DownstreamPort;
PCIE_COMM_CLK_DATA PcieCommClkData;
PcieCommClkData.ScanData.StdHeader = GnbLibGetHeader (Pcie);
PcieCommClkData.ScanData.GnbScanCallback = PcieCommClkCfgCallback;
DownstreamPort = Engine->Type.Port.Address;
if (!PcieConfigIsSbPcieEngine (Engine) && PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieCommClkData.ScanData);
}
}
VOID
STATIC
PcieMidPortCharacterizationCallbackKV (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_SUBLINK_INFO *SublinkInfo;
PCIe_WRAPPER_INFO *WrapperInfo;
PCIe_ASPM_LATENCY_INFO LinkLatencyInfo;
DxFxxE4_xA4_STRUCT DxFxxE4_xA4;
SublinkInfo = &(((PCIe_INFO_BUFFER *)Buffer)->SublinkInfo[MIN (Engine->EngineData.StartLane, Engine->EngineData.EndLane) / 4]);
WrapperInfo = &(((PCIe_INFO_BUFFER *)Buffer)->WrapperInfo[PcieConfigGetParentWrapper (Engine)->WrapId]);
LinkLatencyInfo.MaxL1ExitLatency = 255;
LinkLatencyInfo.MaxL0sExitLatency = 255;
// Count x1/x2 GPP port on each sublink
if (ABS (Engine->EngineData.StartLane - Engine->EngineData.EndLane) <= 2) {
SublinkInfo->GppPortCount += 1;
}
// Determine max gen capability of this engine and sublink
if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
// Port is trained, use device capability
DxFxxE4_xA4.Value = PciePortRegisterRead (Engine, DxFxxE4_xA4_ADDRESS, Pcie);
if (DxFxxE4_xA4.Field.LcOtherSideSupportsGen2 == 1) {
SublinkInfo->MaxGenCapability = Gen2;
}
// Determine minimum L1 exit latency for this engine
PcieAspmGetMinExitLatencyV5 (Engine->Type.Port.Address, &LinkLatencyInfo, GnbLibGetHeader (Pcie));
if (LinkLatencyInfo.MaxL1ExitLatency < WrapperInfo->MinAspmL1ExitLatency) {
WrapperInfo->MinAspmL1ExitLatency = LinkLatencyInfo.MaxL1ExitLatency;
}
} else {
// Hotplug port - use max supported speed
if (Engine->Type.Port.PortData.LinkSpeedCapability > SublinkInfo->MaxGenCapability) {
SublinkInfo->MaxGenCapability = Engine->Type.Port.PortData.LinkSpeedCapability;
}
}
}
VOID
STATIC
GnbIommuMidInitCheckGfxPciePorts (
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_WRAPPER_CONFIG *WrapperList;
BOOLEAN GfxPciePortUsed;
D0F2xF4_x57_STRUCT D0F2xF4_x57;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInitCheckGfxPciePorts Enter\n");
GfxPciePortUsed = FALSE;
WrapperList = PcieConfigGetChildWrapper (Pcie);
ASSERT (WrapperList != NULL);
if (WrapperList->WrapId == GFX_WRAP_ID) {
PCIe_ENGINE_CONFIG *EngineList;
EngineList = PcieConfigGetChildEngine (WrapperList);
while (EngineList != NULL) {
if (PcieConfigIsPcieEngine (EngineList)) {
IDS_HDT_CONSOLE (GNB_TRACE, "Checking Gfx ports device number %x\n", EngineList->Type.Port.NativeDevNumber);
if (PcieConfigCheckPortStatus (EngineList, INIT_STATUS_PCIE_TRAINING_SUCCESS) ||
((EngineList->Type.Port.PortData.LinkHotplug != HotplugDisabled) && (EngineList->Type.Port.PortData.LinkHotplug != HotplugInboard))) {
// GFX PCIe ports beeing used
GfxPciePortUsed = TRUE;
IDS_HDT_CONSOLE (GNB_TRACE, "GFX PCIe ports beeing used\n");
break;
}
}
EngineList = PcieLibGetNextDescriptor (EngineList);
}
}
if (!GfxPciePortUsed) {
//D0F2xF4_x57.Field.L1ImuPcieGfxDis needs to be set
GnbRegisterReadTN (D0F2xF4_x57_TYPE, D0F2xF4_x57_ADDRESS, &D0F2xF4_x57.Value, 0, GnbLibGetHeader (Pcie));
D0F2xF4_x57.Field.L1ImuPcieGfxDis = 1;
GnbRegisterWriteTN (D0F2xF4_x57_TYPE, D0F2xF4_x57_ADDRESS, &D0F2xF4_x57.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
}
IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInitCheckGfxPciePorts Exit\n");
}
VOID
STATIC
PcieMidPortInitCallbackKV (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
DxFxx68_STRUCT DxFxx68;
D0F0xE4_PIF_0012_STRUCT D0F0xE4_PIF_0012;
PCIe_SUBLINK_INFO *SublinkInfo;
PCIe_WRAPPER_INFO *WrapperInfo;
PCIe_WRAPPER_CONFIG *Wrapper;
CPU_LOGICAL_ID LogicalId;
UINT8 Count;
UINT8 Nibble;
PciePortProgramRegisterTable (PortInitMidTableKV.Table, PortInitMidTableKV.Length, Engine, TRUE, Pcie);
if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
PcieEnableSlotPowerLimitV5 (Engine, Pcie);
if (GnbFmCheckIommuPresent ((GNB_HANDLE*) PcieConfigGetParentSilicon (Engine), GnbLibGetHeader (Pcie))) {
PcieInitPortForIommuV4 (Engine, Pcie);
}
// After GFX link is trained up and before ASPM is enabled, AGESA needs to check link width,
// if it equals to x16, then apply the following change to GFX port:
// Per port register 0xA1 - PCIE LC TRAINING CONTROL, bit16 - LC_EXTEND_WAIT_FOR_SKP = 1
GnbLibPciRead (
Engine->Type.Port.Address.AddressValue | DxFxx68_ADDRESS,
AccessWidth32,
&DxFxx68,
GnbLibGetHeader (Pcie)
);
if (DxFxx68.Field.NegotiatedLinkWidth == 16) {
PciePortRegisterRMW (
Engine,
DxFxxE4_xA1_ADDRESS,
DxFxxE4_xA1_LcExtendWaitForSkp_MASK,
(1 << DxFxxE4_xA1_LcExtendWaitForSkp_OFFSET),
TRUE,
Pcie
);
}
}
Wrapper = PcieConfigGetParentWrapper (Engine);
SublinkInfo = &(((PCIe_INFO_BUFFER *)Buffer)->SublinkInfo[MIN (Engine->EngineData.StartLane, Engine->EngineData.EndLane) / 4]);
WrapperInfo = &(((PCIe_INFO_BUFFER *)Buffer)->WrapperInfo[Wrapper->WrapId]);
GetLogicalIdOfCurrentCore (&LogicalId, (AMD_CONFIG_PARAMS *)Pcie->StdHeader);
// Check if this CPU is KV A0
// UBTS468566
if ((LogicalId.Revision & AMD_F15_KV_A0) != 0) {
Count = SublinkInfo->GppPortCount;
IDS_HDT_CONSOLE (GNB_TRACE, "x1x2 PortCount = %02x\n", Count);
if (Count == 2) {
// If number of GPP ports under the same sublink is 2, Delay L1 Exit (prolong minimum time spent in L1)
PciePortRegisterRMW (
Engine,
DxFxxE4_xA0_ADDRESS,
DxFxxE4_xA0_LcDelayCount_MASK |
DxFxxE4_xA0_LcDelayL1Exit_MASK,
(0 << DxFxxE4_xA0_LcDelayCount_OFFSET) |
(1 << DxFxxE4_xA0_LcDelayL1Exit_OFFSET),
TRUE,
Pcie
);
} else if (Count > 2) {
// If number of GPP ports > 2
if (SublinkInfo->MaxGenCapability > Gen1) {
// If at least 1 GPP is Gen2 capable, Disable PLL Power down feature
Wrapper = PcieConfigGetParentWrapper (Engine);
Nibble = (UINT8) ((MIN (Engine->EngineData.StartLane, Engine->EngineData.EndLane) % 8) / 4);
// Only PSD and PPD can have x1/x2 links, so we assume that PIF number is always 0
D0F0xE4_PIF_0012.Value = PcieRegisterRead (
Wrapper,
PIF_SPACE (Wrapper->WrapId, 0, D0F0xE4_PIF_0012_ADDRESS + Nibble),
Pcie
);
D0F0xE4_PIF_0012.Field.PllPowerStateInOff = PifPowerStateL0;
D0F0xE4_PIF_0012.Field.PllPowerStateInTxs2 = PifPowerStateL0;
PcieRegisterWrite (
Wrapper,
PIF_SPACE (Wrapper->WrapId, 0, D0F0xE4_PIF_0012_ADDRESS + Nibble),
D0F0xE4_PIF_0012.Value,
TRUE,
Pcie
);
} else {
// All ports are only Gen1
PciePortRegisterRMW (
Engine,
DxFxxE4_xC0_ADDRESS,
DxFxxE4_xC0_StrapMedyTSxCount_MASK,
0x2 << DxFxxE4_xC0_StrapMedyTSxCount_OFFSET,
TRUE,
Pcie
);
}
}
}
PcieRegisterRMW (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0802_ADDRESS + (0x100 * Engine->Type.Port.PortId)),
D0F0xE4_WRAP_0802_StrapBifL1ExitLatency_MASK,
(WrapperInfo->L1ExitLatencyValue << D0F0xE4_WRAP_0802_StrapBifL1ExitLatency_OFFSET),
TRUE,
Pcie
);
if (WrapperInfo->DisableL1OnWrapper == TRUE) {
Engine->Type.Port.PortData.LinkAspm &= ~(AspmL1);
}
PcieEnableAspm (Engine, Pcie);
}
VOID
STATIC
PcieAlibUpdatePciePortDataCallback (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
_ALIB_PORT_DATA *PortData;
PortData = &((ALIB_DATA *) Buffer)->PortData[Engine->Type.Port.PcieBridgeId].PortData;
if (PcieConfigIsEngineAllocated (Engine) && (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS))) {
//
// Various speed capability
//
PortData->PciePortMaxSpeed = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_MAX, Engine);
PortData->PciePortCurSpeed = (UINT8) PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine);
PortData->PciePortDcSpeed = PcieGen1;
PortData->PciePortAcSpeed = PortData->PciePortMaxSpeed;
if (Pcie->PsppPolicy == PsppBalanceLow) {
PortData->PciePortAcSpeed = PcieGen1;
}
if (PcieConfigIsSbPcieEngine (Engine)) {
PortData->PcieSbPort = 0x1;
PortData->PciePortAcSpeed = PortData->PciePortMaxSpeed;
}
if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode != 0) {
PortData->PcieLinkSafeMode = 0x1;
PortData->PcieLocalOverrideSpeed = Engine->Type.Port.PortData.MiscControls.LinkSafeMode;
}
//
// various port capability
//
PortData->StartPhyLane = (UINT8) Engine->EngineData.StartLane;
PortData->EndPhyLane = (UINT8) Engine->EngineData.EndLane;
PortData->StartCoreLane = (UINT8) Engine->Type.Port.StartCoreLane;
PortData->EndCoreLane = (UINT8) Engine->Type.Port.EndCoreLane;
PortData->PortId = Engine->Type.Port.PortId;
PortData->LinkHotplug = Engine->Type.Port.PortData.LinkHotplug;
PortData->PciDev = (UINT8) Engine->Type.Port.Address.Address.Device;
PortData->PciFun = (UINT8) Engine->Type.Port.Address.Address.Function;
} else {
PortData->PciePortMaxSpeed = PcieGen1;
PortData->PciePortCurSpeed = PcieGen1;
PortData->PciePortDcSpeed = PcieGen1;
PortData->PciePortAcSpeed = PcieGen1;
PortData->PcieLocalOverrideSpeed = PcieGen1;
}
}
UINT32
PcieUtilGetEngineLaneBitMap (
IN UINT32 IncludeLaneType,
IN UINT32 ExcludeLaneType,
IN PCIe_ENGINE_CONFIG *Engine
)
{
UINT32 LaneBitmap;
LaneBitmap = 0;
if (IncludeLaneType & LANE_TYPE_PCIE_LANES) {
if (IncludeLaneType & LANE_TYPE_PCIE_CORE_CONFIG) {
LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyConfig, Engine);
}
if (IncludeLaneType & LANE_TYPE_PCIE_CORE_ALLOC) {
LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine);
}
if (IncludeLaneType & (LANE_TYPE_PCIE_CORE_ACTIVE | LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE)) {
if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_PORT_IN_COMPLIANCE)) {
LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine);
} else if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
if (IncludeLaneType & LANE_TYPE_PCIE_CORE_ALLOC_ACTIVE) {
LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine);
} else {
LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyActive, Engine);
}
}
}
if ((IncludeLaneType & LANE_TYPE_PCIE_SB_CORE_CONFIG) && PcieConfigIsSbPcieEngine (Engine)) {
LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyConfig, Engine);
}
if ((IncludeLaneType & LANE_TYPE_PCIE_CORE_HOTPLUG) && (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled)) {
LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeCore, LanePropertyAllocated, Engine);
}
if (IncludeLaneType & LANE_TYPE_PCIE_PHY) {
LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypePhy, LanePropertyAllocated, Engine);
}
if (IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE) {
LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine);
}
if (IncludeLaneType & (LANE_TYPE_PCIE_PHY_NATIVE_ACTIVE | LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE)) {
if (Engine->Type.Port.PortData.LinkHotplug == HotplugEnhanced || PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_PORT_IN_COMPLIANCE)) {
LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine);
} else if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) {
if (IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE) {
LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine);
} else {
LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyActive, Engine);
}
}
}
if ((IncludeLaneType & LANE_TYPE_PCIE_PHY_NATIVE_HOTPLUG) && (Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled)) {
LaneBitmap |= PcieUtilGetPcieEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine);
}
}
if (IncludeLaneType & LANE_TYPE_DDI_LANES) {
if (IncludeLaneType & LANE_TYPE_DDI_PHY) {
LaneBitmap |= PcieUtilGetDdiEngineLaneBitMap (LaneTypePhy, LanePropertyAllocated, Engine);
}
if (IncludeLaneType & LANE_TYPE_DDI_PHY_NATIVE) {
LaneBitmap |= PcieUtilGetDdiEngineLaneBitMap (LaneTypeNativePhy, LanePropertyAllocated, Engine);
}
if (IncludeLaneType & LANE_TYPE_DDI_PHY_NATIVE_ACTIVE) {
LaneBitmap |= PcieUtilGetDdiEngineLaneBitMap (LaneTypeNativePhy, LanePropertyActive, Engine);
}
}
if (ExcludeLaneType != 0) {
LaneBitmap &= (~PcieUtilGetEngineLaneBitMap (ExcludeLaneType, 0, Engine));
}
return LaneBitmap;
}
