/**
* Various initialization needed prior topology and configuration initialization
*
*
*
* @param[in] Pcie Pointer to global PCIe configuration
*
*/
VOID
PcieFmPreInit (
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT32 Index;
PCIe_SILICON_CONFIG *Silicon;
Silicon = PcieConfigGetChildSilicon (&Pcie->ComplexList[0]);
PcieConfigRunProcForAllWrappers (
DESCRIPTOR_ALL_WRAPPERS,
PcieFmPhyLetPllPersonalityInitCallback,
NULL,
Pcie
);
PcieFmOscInitPhyForGen2 (Pcie);
PcieConfigRunProcForAllWrappers (
DESCRIPTOR_PCIE_WRAPPER,
PcieFmPhyLaneInitInitCallback,
NULL,
Pcie
);
for (Index = 0; Index < (sizeof (PcieInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY)); Index++) {
PcieSiliconRegisterRMW (
Silicon,
PcieInitTable[Index].Reg,
PcieInitTable[Index].Mask,
PcieInitTable[Index].Data,
FALSE,
Pcie
);
}
// Set PCIe SSID.
PcieSiliconRegisterRMW (
Silicon,
WRAP_SPACE (0, D0F0xE4_WRAP_8002_ADDRESS),
D0F0xE4_WRAP_8002_PcieWrapScratch_MASK,
UserOptions.CfgGnbPcieSSID << D0F0xE4_WRAP_8002_PcieWrapScratch_OFFSET,
FALSE,
Pcie
);
PcieSiliconRegisterRMW (
Silicon,
WRAP_SPACE (1, D0F0xE4_WRAP_8002_ADDRESS),
D0F0xE4_WRAP_8002_PcieWrapScratch_MASK,
UserOptions.CfgGnbPcieSSID << D0F0xE4_WRAP_8002_PcieWrapScratch_OFFSET,
FALSE,
Pcie
);
}
/**
* Control port visibility in PCI config space
*
*
* @param[in] Control Make port Hide/Unhide ports
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PciePortsVisibilityControl (
IN PCIE_PORT_VISIBILITY Control,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_COMPLEX_CONFIG *ComplexList;
ComplexList = &Pcie->ComplexList[0];
while (ComplexList != NULL) {
PCIe_SILICON_CONFIG *SiliconList;
SiliconList = PcieConfigGetChildSilicon (ComplexList);
while (SiliconList != NULL) {
PcieFmPortVisabilityControl (Control, SiliconList, Pcie);
SiliconList = PcieLibGetNextDescriptor (SiliconList);
}
ComplexList = PcieLibGetNextDescriptor (ComplexList);
}
}
AGESA_STATUS
PcieMapTopologyOnComplex (
IN PCIe_COMPLEX_DESCRIPTOR *ComplexDescriptor,
IN PCIe_COMPLEX_CONFIG *Complex,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_SILICON_CONFIG *Silicon;
PCIe_WRAPPER_CONFIG *Wrapper;
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
AgesaStatus = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnComplex Enter\n");
Silicon = PcieConfigGetChildSilicon (Complex);
while (Silicon != NULL) {
Wrapper = PcieConfigGetChildWrapper (Silicon);
while (Wrapper != NULL) {
Status = PcieMapTopologyOnWrapper (ComplexDescriptor, Wrapper, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_ERROR) {
PcieConfigDisableAllEngines (PciePortEngine | PcieDdiEngine, Wrapper);
IDS_HDT_CONSOLE (PCIE_MISC, " ERROR! Fail to map topology on %s Wrapper\n",
PcieFmDebugGetWrapperNameString (Wrapper)
);
ASSERT (FALSE);
}
Wrapper = PcieLibGetNextDescriptor (Wrapper);
}
Status = PcieMapPortsPciAddresses (Silicon, Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
Silicon = PcieLibGetNextDescriptor (Silicon);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapTopologyOnComplex Exit [%x]\n", AgesaStatus);
return AgesaStatus;
}
/**
* Helper function to dump configuration to debug out
*
*
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
PcieConfigDebugDump (
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_SILICON_CONFIG *SiliconList;
PCIe_WRAPPER_CONFIG *WrapperList;
PCIe_COMPLEX_CONFIG *ComplexList;
ComplexList = (PCIe_COMPLEX_CONFIG *) PcieConfigGetChild (DESCRIPTOR_COMPLEX, &Pcie->Header);
IDS_HDT_CONSOLE (PCIE_MISC, "<-------------- PCIe Config Start------------>\n");
IDS_HDT_CONSOLE (PCIE_MISC, " PSPP Policy - %s\n",
(Pcie->PsppPolicy == PsppPowerSaving) ? "Power Saving" :
(Pcie->PsppPolicy == PsppBalanceHigh) ? "Balance-High" : (
(Pcie->PsppPolicy == PsppBalanceLow) ? "Balance-Low" : (
(Pcie->PsppPolicy == PsppPerformance) ? "Performance" : (
(Pcie->PsppPolicy == PsppDisabled) ? "Disabled" : "Unknown")))
);
IDS_HDT_CONSOLE (PCIE_MISC, " GFX Workaround - %s\n",
(Pcie->GfxCardWorkaround == 0) ? "Disabled" : "Enabled"
);
IDS_HDT_CONSOLE (PCIE_MISC, " LinkL0Pooling - %dus\n",
Pcie->LinkL0Pooling
);
IDS_HDT_CONSOLE (PCIE_MISC, " LinkGpioResetAssertionTime - %dus\n",
Pcie->LinkGpioResetAssertionTime
);
IDS_HDT_CONSOLE (PCIE_MISC, " LinkReceiverDetectionPooling - %dus\n",
Pcie->LinkReceiverDetectionPooling
);
IDS_HDT_CONSOLE (PCIE_MISC, " Training Algorythm - %s\n",
(Pcie->TrainingAlgorithm == PcieTrainingStandard) ? "PcieTrainingStandard" : (
(Pcie->TrainingAlgorithm == PcieTrainingDistributed) ? "PcieTrainingDistributed" : "Unknown")
);
while (ComplexList != NULL) {
IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Complex Config Start ---------->\n");
IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", ComplexList->Header.DescriptorFlags);
IDS_HDT_CONSOLE (PCIE_MISC, " Socket ID - %d\n", ComplexList->SocketId);
SiliconList = PcieConfigGetChildSilicon (ComplexList);
while (SiliconList != NULL) {
IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Silicon Config Start -------->\n");
IDS_HDT_CONSOLE (PCIE_MISC, " Descriptor Flags - 0x%08x\n", SiliconList->Header.DescriptorFlags);
IDS_HDT_CONSOLE (PCIE_MISC, " Silicon ID - %d\n", SiliconList->SiliconId);
IDS_HDT_CONSOLE (PCIE_MISC, " Node ID - %d\n", SiliconList->NodeId);
IDS_HDT_CONSOLE (PCIE_MISC, " Host PCI Address - %d:%d:%d\n",
SiliconList->Address.Address.Bus,
SiliconList->Address.Address.Device,
SiliconList->Address.Address.Function
);
WrapperList = PcieConfigGetChildWrapper (SiliconList);
while (WrapperList != NULL) {
PcieConfigWrapperDebugDump (WrapperList);
WrapperList = PcieLibGetNextDescriptor (WrapperList);
}
IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Silicon Config End ---------->\n");
SiliconList = PcieLibGetNextDescriptor (SiliconList);
}
IDS_HDT_CONSOLE (PCIE_MISC, " <---------- Complex Config End ------------>\n");
ComplexList = PcieLibGetNextDescriptor (ComplexList);
}
IDS_HDT_CONSOLE (PCIE_MISC, "<-------------- PCIe Config End-------------->\n");
}
AGESA_STATUS
PcieConfigurationInit (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
PCIe_PLATFORM_CONFIG *Pcie;
PCIe_SILICON_CONFIG *Silicon;
UINT8 SocketId;
UINTN CurrentComplexesDataLength;
UINTN ComplexesDataLength;
UINT8 ComplexIndex;
VOID *Buffer;
ComplexesDataLength = 0;
Status = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationInit Enter\n");
for (SocketId = 0; SocketId < GetPlatformNumberOfSockets (); SocketId++) {
if (IsProcessorPresent (SocketId, StdHeader)) {
Status = PcieFmGetComplexDataLength (SocketId, &CurrentComplexesDataLength, StdHeader);
ASSERT (Status == AGESA_SUCCESS);
ComplexesDataLength += CurrentComplexesDataLength;
}
}
ComplexIndex = 0;
Pcie = GnbAllocateHeapBufferAndClear (AMD_PCIE_COMPLEX_DATA_HANDLE, sizeof (PCIe_PLATFORM_CONFIG) + ComplexesDataLength, StdHeader);
ASSERT (Pcie != NULL);
if (Pcie != NULL) {
PcieConfigAttachChild (&Pcie->Header, &Pcie->ComplexList[ComplexIndex].Header);
PcieConfigSetDescriptorFlags (Pcie, DESCRIPTOR_PLATFORM | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_TOPOLOGY);
Buffer = (UINT8 *) (Pcie) + sizeof (PCIe_PLATFORM_CONFIG);
for (SocketId = 0; SocketId < GetPlatformNumberOfSockets (); SocketId++) {
if (IsProcessorPresent (SocketId, StdHeader)) {
Pcie->ComplexList[ComplexIndex].SocketId = SocketId;
//Attache Comples to Silicon which will be created by PcieFmBuildComplexConfiguration
PcieConfigAttachChild (&Pcie->ComplexList[ComplexIndex].Header, &((PCIe_SILICON_CONFIG *) Buffer)->Header);
//Attach Comples to Pcie
PcieConfigAttachParent (&Pcie->Header, &Pcie->ComplexList[ComplexIndex].Header);
PcieConfigSetDescriptorFlags (&Pcie->ComplexList[ComplexIndex], DESCRIPTOR_COMPLEX | DESCRIPTOR_TERMINATE_LIST | DESCRIPTOR_TERMINATE_GNB | DESCRIPTOR_TERMINATE_TOPOLOGY);
PcieFmBuildComplexConfiguration (SocketId, Buffer, StdHeader);
Silicon = PcieConfigGetChildSilicon (&Pcie->ComplexList[ComplexIndex]);
while (Silicon != NULL) {
PcieConfigAttachParent (&Pcie->ComplexList[ComplexIndex].Header, &Silicon->Header);
GetNodeId (SocketId, Silicon->SiliconId, &Silicon->NodeId, StdHeader);
GnbFmGetLinkId ((GNB_HANDLE*) Silicon, &Silicon->LinkId, StdHeader);
Silicon = (PCIe_SILICON_CONFIG *) PcieConfigGetNextTopologyDescriptor (Silicon, DESCRIPTOR_TERMINATE_TOPOLOGY);
}
if (ComplexIndex > 0) {
PcieConfigAttachComplexes (&Pcie->ComplexList[ComplexIndex - 1], &Pcie->ComplexList[ComplexIndex]);
}
PcieFmGetComplexDataLength (SocketId, &CurrentComplexesDataLength, StdHeader);
Buffer = (VOID *) ((UINT8 *) Buffer + CurrentComplexesDataLength);
ComplexIndex++;
}
}
} else {
Status = AGESA_FATAL;
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieConfigurationInit Exit [0x%x]\n", Status);
return Status;
}
