VOID
PcieSetPortPciAddressMapML (
IN PCIe_SILICON_CONFIG *Silicon
)
{
UINT8 Index;
UINT8 DevFuncIndex;
UINT8 PortDevMap [sizeof (DefaultPortDevMapML)];
PCIe_PLATFORM_CONFIG *Pcie;
D0F0x64_x30_STRUCT D0F0x64_x30;
Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Silicon->Header);
LibAmdMemCopy (&PortDevMap[0], &DefaultPortDevMapML[0], sizeof (DefaultPortDevMapML), GnbLibGetHeader (Pcie));
for (Index = 0; Index < sizeof (((ML_COMPLEX_CONFIG *) Silicon)->FmSilicon.PortDevMap); ++Index) {
if (((ML_COMPLEX_CONFIG *) Silicon)->FmSilicon.PortDevMap[Index] != 0) {
for (DevFuncIndex = 0; DevFuncIndex < sizeof (((ML_COMPLEX_CONFIG *) Silicon)->FmSilicon.PortDevMap); ++DevFuncIndex) {
if (PortDevMap[DevFuncIndex] == ((ML_COMPLEX_CONFIG *) Silicon)->FmSilicon.PortDevMap[Index]) {
PortDevMap[DevFuncIndex] = 0;
break;
}
}
}
}
for (Index = 0; Index < sizeof (((ML_COMPLEX_CONFIG *) Silicon)->FmSilicon.PortDevMap); ++Index) {
if (((ML_COMPLEX_CONFIG *) Silicon)->FmSilicon.PortDevMap[Index] == 0) {
for (DevFuncIndex = 0; DevFuncIndex < sizeof (((ML_COMPLEX_CONFIG *) Silicon)->FmSilicon.PortDevMap); ++DevFuncIndex) {
if (PortDevMap[DevFuncIndex] != 0) {
((ML_COMPLEX_CONFIG *) Silicon)->FmSilicon.PortDevMap[Index] = PortDevMap[DevFuncIndex];
PortDevMap[DevFuncIndex] = 0;
break;
}
}
}
GnbRegisterReadML ((GNB_HANDLE *) Silicon, D0F0x64_x30_TYPE, D0F0x64_x30_ADDRESS + Index, &D0F0x64_x30.Value, 0, GnbLibGetHeader (Pcie));
D0F0x64_x30.Field.DevFnMap = ((ML_COMPLEX_CONFIG *) Silicon)->FmSilicon.PortDevMap[Index];
GnbRegisterWriteML ((GNB_HANDLE *) Silicon, D0F0x64_x30_TYPE, D0F0x64_x30_ADDRESS + Index, &D0F0x64_x30.Value, 0, GnbLibGetHeader (Pcie));
}
}
AGESA_STATUS
PcieFmMapPortPciAddress (
IN PCIe_ENGINE_CONFIG *Engine
)
{
PCIe_WRAPPER_CONFIG *Wrapper;
PCIe_PLATFORM_CONFIG *Pcie;
UINT64 ConfigurationSignature;
Wrapper = PcieConfigGetParentWrapper (Engine);
Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header);
if (Wrapper->WrapId == GPP_WRAP_ID) {
ConfigurationSignature = PcieConfigGetConfigurationSignature (Wrapper, Engine->Type.Port.CoreId);
if ((ConfigurationSignature == GPP_CORE_x4x2x1x1_ST) || (ConfigurationSignature == GPP_CORE_x4x2x2_ST)) {
//Enable device remapping
GnbLibPciIndirectRMW (
MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS),
D0F0x64_x20_ADDRESS | IOC_WRITE_ENABLE,
AccessS3SaveWidth32,
~(UINT32) (1 << D0F0x64_x20_IocPcieDevRemapDis_OFFSET),
0x0,
GnbLibGetHeader (Pcie)
);
}
}
if (Engine->Type.Port.PortData.DeviceNumber == 0 && Engine->Type.Port.PortData.FunctionNumber == 0) {
Engine->Type.Port.PortData.DeviceNumber = Engine->Type.Port.NativeDevNumber;
Engine->Type.Port.PortData.FunctionNumber = Engine->Type.Port.NativeFunNumber;
return AGESA_SUCCESS;
}
if (Engine->Type.Port.PortData.DeviceNumber == Engine->Type.Port.NativeDevNumber &&
Engine->Type.Port.PortData.FunctionNumber == Engine->Type.Port.NativeFunNumber) {
return AGESA_SUCCESS;
}
return AGESA_ERROR;
}
AGESA_STATUS
PcieMapPortPciAddressTN (
IN PCIe_ENGINE_CONFIG *Engine
)
{
AGESA_STATUS Status;
TN_COMPLEX_CONFIG *ComplexConfig;
PCIe_PLATFORM_CONFIG *Pcie;
UINT8 PortDevMap[6];
UINT8 FreeDevMap[6];
UINT8 PortIndex;
UINT8 EnginePortIndex;
UINT8 FreeIndex;
D0F0x64_x20_STRUCT D0F0x64_x20;
D0F0x64_x21_STRUCT D0F0x64_x21;
Status = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapPortPciAddressTN Enter\n");
if (Engine->Type.Port.PortData.DeviceNumber == 0 && Engine->Type.Port.PortData.FunctionNumber == 0) {
Engine->Type.Port.PortData.DeviceNumber = Engine->Type.Port.NativeDevNumber;
Engine->Type.Port.PortData.FunctionNumber = Engine->Type.Port.NativeFunNumber;
}
if (!PcieConfigIsSbPcieEngine (Engine)) {
ComplexConfig = (TN_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_SILICON, &Engine->Header);
Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Engine->Header);
LibAmdMemFill (&FreeDevMap[0], 0x0, sizeof (FreeDevMap), GnbLibGetHeader (Pcie));
LibAmdMemCopy (&PortDevMap[0], &ComplexConfig->FmSilicon.PortDevMap, sizeof (PortDevMap), GnbLibGetHeader (Pcie));
for (PortIndex = 0; PortIndex < sizeof (PortDevMap); PortIndex++) {
if (PortDevMap[PortIndex] != 0) {
FreeDevMap[PortDevMap[PortIndex] - 2] = 1;
}
}
EnginePortIndex = Engine->Type.Port.PortData.DeviceNumber - 2;
if (FreeDevMap[EnginePortIndex] == 0) {
// Dev number not yet allocated
ComplexConfig->FmSilicon.PortDevMap[Engine->Type.Port.NativeDevNumber - 2] = Engine->Type.Port.PortData.DeviceNumber;
FreeDevMap[EnginePortIndex] = 1;
PortDevMap[Engine->Type.Port.NativeDevNumber - 2] = Engine->Type.Port.PortData.DeviceNumber;
for (PortIndex = 0; PortIndex < sizeof (PortDevMap); PortIndex++) {
if (PortDevMap[PortIndex] == 0) {
for (FreeIndex = 0; FreeIndex < sizeof (FreeDevMap); FreeIndex++) {
if (FreeDevMap[FreeIndex] == 0) {
FreeDevMap[FreeIndex] = 1;
break;
}
}
PortDevMap[PortIndex] = FreeIndex + 2;
}
}
GnbRegisterReadTN (D0F0x64_x20_TYPE, D0F0x64_x20_ADDRESS, &D0F0x64_x20, 0, GnbLibGetHeader (Pcie));
D0F0x64_x20.Field.ProgDevMapEn = 0;
GnbRegisterWriteTN (D0F0x64_x20_TYPE, D0F0x64_x20_ADDRESS, &D0F0x64_x20, 0, GnbLibGetHeader (Pcie));
GnbRegisterReadTN (D0F0x64_x21_TYPE, D0F0x64_x21_ADDRESS, &D0F0x64_x21, 0, GnbLibGetHeader (Pcie));
D0F0x64_x21.Field.GfxPortADevmap = PortDevMap[2 - 2];
D0F0x64_x21.Field.GfxPortBDevmap = PortDevMap[3 - 2];
D0F0x64_x20.Field.GppPortBDevmap = PortDevMap[4 - 2];
D0F0x64_x20.Field.GppPortCDevmap = PortDevMap[5 - 2];
D0F0x64_x20.Field.GppPortDDevmap = PortDevMap[6 - 2];
D0F0x64_x20.Field.GppPortEDevmap = PortDevMap[7 - 2];
D0F0x64_x20.Field.ProgDevMapEn = 0x1;
GnbRegisterWriteTN (D0F0x64_x20_TYPE, D0F0x64_x20_ADDRESS, &D0F0x64_x20, 0, GnbLibGetHeader (Pcie));
GnbRegisterWriteTN (D0F0x64_x21_TYPE, D0F0x64_x21_ADDRESS, &D0F0x64_x21, 0, GnbLibGetHeader (Pcie));
D0F0x64_x20.Field.ProgDevMapEn = 1;
GnbRegisterWriteTN (D0F0x64_x20_TYPE, D0F0x64_x20_ADDRESS, &D0F0x64_x20, 0, GnbLibGetHeader (Pcie));
} else {
IDS_HDT_CONSOLE (GNB_TRACE, " Fail device %d to port %d\n", Engine->Type.Port.PortData.DeviceNumber, Engine->Type.Port.NativeDevNumber);
Status = AGESA_ERROR;
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMapPortPciAddressTN Exit [0x%x]\n", Status);
return Status;
}
