AGESA_STATUS
STATIC
PcieEarlyPortInitTN (
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS Status;
Status = AGESA_SUCCESS;
// Leave all device in Presence Detect Presence state for distributed training will be completed at PciePortPostEarlyInit
if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) {
Pcie->TrainingExitState = LinkStateResetExit;
}
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PcieEarlyPortInitCallbackTN,
NULL,
Pcie
);
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_DDI_ENGINE,
DdiEarlyPortInitCallbackTN,
NULL,
Pcie
);
IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_EARLY_PORT_CONFIG, Pcie, (AMD_CONFIG_PARAMS *)Pcie->StdHeader);
return Status;
}
/**
* Enumerate audio endpoint in all display connectors.
*
*
*
* @param[in] Gfx Gfx configuration info
* @param[in, out] AudioEPCount Total Audio endpoint number
* @retval AGESA_STATUS
*/
AGESA_STATUS
GfxIntAudioEPEnumV5 (
IN GFX_PLATFORM_CONFIG *Gfx,
IN OUT UINT8 *AudioEPCount
)
{
UINT8 NumAudioEp;
AGESA_STATUS Status;
PCIe_PLATFORM_CONFIG *Pcie;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntAudioEPEnumV5 Enter\n");
NumAudioEp = 0;
Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie);
if ((Status == AGESA_SUCCESS) && (Gfx->GnbHdAudio != 0)) {
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL,
GfxIntAudioEpEnumCallback,
&NumAudioEp,
Pcie
);
if (Gfx->GnbRemoteDisplaySupport) {
NumAudioEp++;
}
}
*AudioEPCount = NumAudioEp;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntAudioEPEnumV5 Exit\n");
return Status;
}
AGESA_STATUS
PcieEdpPortPowerCheckCZ (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
GMMx1206C_STRUCT GMMx1206C;
BOOLEAN EdpPresent;
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
PCIe_PLATFORM_CONFIG *Pcie;
AgesaStatus = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieEdpPortPowerCheckCZ Enter\n");
Status = PcieLocateConfigurationData (StdHeader, &Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_SUCCESS) {
EdpPresent = FALSE;
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL,
DdiEdpPortDetectCallbackCZ,
(VOID *)&EdpPresent,
Pcie
);
if (EdpPresent == FALSE) {
// Power off
GnbRegisterReadCZ (GnbGetHandle (GnbLibGetHeader (Pcie)), GMMx1206C_TYPE, GMMx1206C_ADDRESS, &GMMx1206C.Value, 0, GnbLibGetHeader (Pcie));
GMMx1206C.Field.LVTMA_PWRSEQ_EN = 0;
GMMx1206C.Field.LVTMA_PWRSEQ_TARGET_STATE = 0;
GMMx1206C.Field.LVTMA_BLON_OVRD = 0;
GnbRegisterWriteCZ (GnbGetHandle (GnbLibGetHeader (Pcie)), GMMx1206C_TYPE, GMMx1206C_ADDRESS, &GMMx1206C.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Pcie));
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidBeforeGfxInitCZ Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
AGESA_STATUS
STATIC
PcieMidPortInitKV (
IN OUT PCIe_INFO_BUFFER *PcieInfoBuffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS Status;
PCIE_LINK_SPEED_CAP GlobalSpeedCap;
Status = AGESA_SUCCESS;
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PcieMidPortInitCallbackKV,
PcieInfoBuffer,
Pcie
);
GlobalSpeedCap = PcieUtilGlobalGenCapability (
PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS | PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS,
Pcie
);
PcieSetVoltageKV (GlobalSpeedCap, Pcie);
return Status;
}
/**
* Enumerate all display connectors with audio capability and configure number of ports
*
*
*
* @param[in] Gfx Gfx configuration info
*/
AGESA_STATUS
GfxIntegratedEnumerateAudioConnectors (
IN GFX_PLATFORM_CONFIG *Gfx
)
{
UINT8 AudioCount;
AGESA_STATUS Status;
GMMx5F50_STRUCT GMMx5F50;
PCIe_PLATFORM_CONFIG *Pcie;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAudioConnectors Enter\n");
Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie);
if ((Status == AGESA_SUCCESS) && (Gfx->GnbHdAudio != 0)) {
AudioCount = 0;
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE,
GfxIntegratedAudioEnumCallback,
&AudioCount,
Pcie
);
if (AudioCount > 4) {
AudioCount = 4;
}
GMMx5F50.Value = 0x00;
GMMx5F50.Field.PortConnectivity = (7 - AudioCount);
GMMx5F50.Field.PortConnectivityOverrideEnable = 1;
GnbRegisterWriteTN (GMMx5F50_TYPE, GMMx5F50_ADDRESS, &GMMx5F50.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx));
}
IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedEnumerateAudioConnectors Exit\n");
return Status;
}
AGESA_STATUS
PcieAlibUpdatePcieData (
IN OUT VOID *DataBuffer,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCIe_PLATFORM_CONFIG *Pcie;
AMD_LATE_PARAMS *LateParamsPtr;
AGESA_STATUS Status;
BOOLEAN DcTdpEnable;
GNB_BUILD_OPTIONS_COMMON *GnbCommonOptions;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdatePcieData Enter\n");
ASSERT (DataBuffer != NULL);
Status = AGESA_SUCCESS;
GnbCommonOptions = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, StdHeader);
if (GnbCommonOptions != NULL) {
DcTdpEnable = GnbCommonOptions->CfgDcTdpEnable;
} else {
GnbCommonOptions = (GNB_BUILD_OPTIONS_COMMON*) GnbFmGnbBuildOptions (StdHeader);
DcTdpEnable = GnbCommonOptions->CfgDcTdpEnable;
}
//
// Locate PCIe platform config
//
if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) {
//
// Update policy data
//
((ALIB_DATA *) DataBuffer)->Data.Data.PsppPolicy = Pcie->PsppPolicy;
//
// Update data for each port
//
PcieConfigRunProcForAllEngines (
DESCRIPTOR_PCIE_ENGINE,
PcieAlibUpdatePciePortDataCallback,
DataBuffer,
Pcie
);
} else {
ASSERT (FALSE);
Status = AGESA_FATAL;
}
LateParamsPtr = (AMD_LATE_PARAMS *) StdHeader;
((ALIB_DATA *) DataBuffer)->Data.Data.DockedTdpHeadroom =
LateParamsPtr->GnbLateConfiguration.DockedTdpHeadroom;
IDS_HDT_CONSOLE (GNB_TRACE, " DockedTdpHeadroom = %02x\n",
LateParamsPtr->GnbLateConfiguration.DockedTdpHeadroom);
IDS_HDT_CONSOLE (GNB_TRACE, " DcTdpEnable = %x\n", DcTdpEnable);
((ALIB_DATA *) DataBuffer)->Data.Data.DcTdpEnable = DcTdpEnable;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdatePcieData Exit\n");
return Status;
}
AGESA_STATUS
GnbCableSafeEntry (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
PCIe_PLATFORM_CONFIG *Pcie;
PCIe_ENGINE_CONFIG *DdiEngineList [MaxHdp];
UINT8 HdpIndex;
UINT8 CurrentIndex;
GNB_CABLE_SAFE_DATA CableSafeData;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbCableSafeEntry Enter\n");
Status = AGESA_SUCCESS;
if (GnbCableSafeIsSupported (StdHeader)) {
if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) {
for (HdpIndex = 0; HdpIndex < MaxHdp; HdpIndex++) {
DdiEngineList[HdpIndex] = NULL;
}
LibAmdMemFill (&CableSafeData, 0, sizeof (CableSafeData), StdHeader);
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_DDI_ENGINE,
GnbCableSafeGetConnectorInfoArrayCallback,
DdiEngineList,
Pcie
);
CurrentIndex = 0;
for (HdpIndex = 0; HdpIndex < MaxHdp; HdpIndex++) {
if (DdiEngineList [HdpIndex] != NULL) {
CableSafeData.Data[HdpIndexTranslationTable[CurrentIndex]] = HdpIndex + 1;
CableSafeData.Data[AuxIndexTranslationTable[CurrentIndex]] = AuxDataTranslationTable [(DdiEngineList [HdpIndex])->Type.Ddi.DdiData.AuxIndex];
IDS_HDT_CONSOLE (NB_MISC, " Index [%d] HDP 0x%02x AUX 0x%02x\n", CurrentIndex, HdpIndex, (DdiEngineList [HdpIndex])->Type.Ddi.DdiData.AuxIndex);
CurrentIndex++;
}
}
CableSafeData.Config.Enable = 0x1;
CableSafeData.Config.DebounceFilter = 0x2;
CableSafeData.Config.SoftPeriod = 0x4;
CableSafeData.Config.Unit = 0x1;
CableSafeData.Config.Period = 0xf424;
NbSmuRcuRegisterWrite (
SMUx0B_x85D0_ADDRESS,
(UINT32*) &CableSafeData,
sizeof (CableSafeData) / sizeof (UINT32),
TRUE,
StdHeader
);
NbSmuServiceRequest (0x05, TRUE, StdHeader);
} else {
Status = AGESA_ERROR;
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "GnbCableSafeEntry Exit [Status = 0x%04x]\n", Status);
return Status;
}
AGESA_STATUS
STATIC
PciePostS3PortInitML (
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS Status;
Status = AGESA_SUCCESS;
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PciePostS3PortInitCallbackML,
NULL,
Pcie
);
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL,
DdiPostPortInitCallbackML,
NULL,
Pcie
);
return Status;
}
AGESA_STATUS
PciePortPostS3Init (
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS Status;
Status = AGESA_SUCCESS;
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PciePortPostS3InitCallback,
NULL,
Pcie
);
return Status;
}
/**
* Assert GPIO port reset.
*
* Transition to LinkStateResetDuration state
*
* @param[in] CurrentEngine Pointer to engine config descriptor
* @param[in] Pcie Pointer to global PCIe configuration
*
*/
VOID
STATIC
PcieTrainingAssertReset (
IN PCIe_ENGINE_CONFIG *CurrentEngine,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_SLOT_RESET_INFO ResetInfo;
ResetInfo.ResetControl = AssertSlotReset;
ResetInfo.ResetId = CurrentEngine->Type.Port.PortData.ResetId;
LibAmdMemCopy (&ResetInfo.StdHeader, GnbLibGetHeader (Pcie), sizeof (AMD_CONFIG_PARAMS), GnbLibGetHeader (Pcie));
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PcieSetResetStateOnEnginesV2,
(VOID *)&CurrentEngine->Type.Port.PortData.ResetId,
Pcie
);
AgesaPcieSlotResetControl (0, &ResetInfo);
}
AGESA_STATUS
PcieAlibUpdatePcieData (
IN OUT VOID *DataBuffer,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCIe_PLATFORM_CONFIG *Pcie;
AMD_LATE_PARAMS *LateParamsPtr;
AGESA_STATUS Status;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdatePcieData Enter\n");
ASSERT (DataBuffer != NULL);
Status = AGESA_SUCCESS;
//
// Locate PCIe platform config
//
if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) {
//
// Update policy data
//
((ALIB_DATA *) DataBuffer)->Data.Data.PsppPolicy = Pcie->PsppPolicy;
//
// Update data for each port
//
PcieConfigRunProcForAllEngines (
DESCRIPTOR_PCIE_ENGINE,
PcieAlibUpdatePciePortDataCallback,
DataBuffer,
Pcie
);
} else {
ASSERT (FALSE);
Status = AGESA_FATAL;
}
LateParamsPtr = (AMD_LATE_PARAMS *) StdHeader;
((ALIB_DATA *) DataBuffer)->Data.Data.DockedTdpHeadroom =
LateParamsPtr->GnbLateConfiguration.DockedTdpHeadroom;
IDS_HDT_CONSOLE (GNB_TRACE, " DockedTdpHeadroom = %02x\n",
LateParamsPtr->GnbLateConfiguration.DockedTdpHeadroom);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdatePcieData Exit\n");
return Status;
}
AGESA_STATUS
PciePortInit (
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS Status;
Status = AGESA_SUCCESS;
// Leave all device in Presence Detect Presence state for distributed training will be completed at PciePortPostEarlyInit
if (Pcie->TrainingAlgorithm == PcieTrainingDistributed) {
Pcie->TrainingExitState = LinkStateResetExit;
}
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PciePortInitCallback,
NULL,
Pcie
);
return Status;
}
AGESA_STATUS
STATIC
PcieMidCharacterizationKV (
IN OUT PCIe_INFO_BUFFER *PcieInfoBuffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS AgesaStatus;
AGESA_STATUS Status;
UINT8 Index;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidCharacterizationKV Enter\n");
AgesaStatus = AGESA_SUCCESS;
// Set initial stats for all PcieInfoBuffer fields
for (Index = 0; Index < NUMBER_OF_SUBLINKS; Index++) {
((PCIe_INFO_BUFFER *) PcieInfoBuffer)->SublinkInfo[Index].GppPortCount = 0;
((PCIe_INFO_BUFFER *) PcieInfoBuffer)->SublinkInfo[Index].MaxGenCapability = Gen1;
}
for (Index = 0; Index < NUMBER_OF_WRAPPERS; Index++) {
((PCIe_INFO_BUFFER *) PcieInfoBuffer)->WrapperInfo[Index].MinAspmL1ExitLatency = 255;
((PCIe_INFO_BUFFER *) PcieInfoBuffer)->WrapperInfo[Index].AnyDevFailPllpdnb = FALSE;
((PCIe_INFO_BUFFER *) PcieInfoBuffer)->WrapperInfo[Index].DisableL1OnWrapper = FALSE;
}
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PcieMidPortCharacterizationCallbackKV,
(VOID *) PcieInfoBuffer,
Pcie
);
Status = PcieConfigRunProcForAllWrappers (
DESCRIPTOR_ALL_WRAPPERS,
PcieMidWrapperCharacterizationCallbackKV,
(VOID *) PcieInfoBuffer,
Pcie);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidCharacterizationKV Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
/*----------------------------------------------------------------------------------------*/
AGESA_STATUS
PcieCommClkCfgInterface (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS AgesaStatus;
PCIe_PLATFORM_CONFIG *Pcie;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieCommClkCfgInterface Enter\n");
AgesaStatus = PcieLocateConfigurationData (StdHeader, &Pcie);
if (AgesaStatus == AGESA_SUCCESS) {
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PcieCommClkCfgPortInitCallback,
NULL,
Pcie
);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PcieCommClkCfgInterface Exit [0x%x]\n", AgesaStatus);
return AgesaStatus;
}
AGESA_STATUS
PcieTraining (
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS Status;
BOOLEAN TrainingComplete;
Status = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTraining Enter\n");
do {
TrainingComplete = TRUE;
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PcieTrainingPortCallback,
&TrainingComplete,
Pcie
);
} while (!TrainingComplete);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTraining Exit [%x]\n", Status);
return Status;
}
/**
* Determine global GEN capability
*
*
* @param[in] Flags global GEN capability flags
* @param[in] Pcie Pointer to global PCIe configuration
*
*/
PCIE_LINK_SPEED_CAP
PcieUtilGlobalGenCapability (
IN UINT32 Flags,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIE_LINK_SPEED_CAP GlobalCapability;
PCIE_GLOBAL_GEN_CAP_WORKSPACE GlobalGenCap;
GlobalGenCap.LinkSpeedCapability = PcieGen1;
GlobalGenCap.Flags = Flags;
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PcieUtilGlobalGenCapabilityCallback,
&GlobalGenCap,
Pcie
);
GlobalCapability = GlobalGenCap.LinkSpeedCapability;
return GlobalCapability;
}
AGESA_STATUS
GnbNbIoapicInterface (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AMD_MID_PARAMS *MidParamsPtr;
AGESA_STATUS Status;
PCIe_PLATFORM_CONFIG *Pcie;
UINT64 GnbNbIoapicAddress;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbNbIoapicInterface Enter\n");
Status = PcieLocateConfigurationData (StdHeader, &Pcie);
if (Status == AGESA_SUCCESS) {
MidParamsPtr = (AMD_MID_PARAMS *) StdHeader;
GnbNbIoapicAddress = MidParamsPtr->GnbMidConfiguration.GnbIoapicAddress;
// For each ENGINE, configure the group, swizzle, and pin per APIC_DEVICE_INFO
PcieConfigRunProcForAllEngines (DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, IoapicInitCallbackV5, NULL, Pcie);
// For each GNB, configure the IOAPIC Enable, ID Size, and SB Feature Enable
Status = PcieConfigRunProcForAllDescriptors (DESCRIPTOR_SILICON, 0, DESCRIPTOR_TERMINATE_TOPOLOGY, IoapicEnableCallbackV5, &GnbNbIoapicAddress, Pcie);
}
IDS_HDT_CONSOLE (GNB_TRACE, "GnbNbIoapicInterface Exit\n");
return Status;
}
STATIC AGESA_STATUS
GnbIommuMidInit (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
PCIe_PLATFORM_CONFIG *Pcie;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInit Enter\n");
Status = PcieLocateConfigurationData (StdHeader, &Pcie);
if (Status == AGESA_SUCCESS) {
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
GnbIommuMidInitOnPortCallback,
NULL,
Pcie
);
}
GnbIommuMidInitCheckGfxPciePorts (Pcie);
IDS_HDT_CONSOLE (GNB_TRACE, "GnbIommuMidInit Exit [0x%x]\n", Status);
return Status;
}
AGESA_STATUS
PcieTrainingV2 (
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
AGESA_STATUS Status;
BOOLEAN TrainingComplete;
IDS_PERF_TIMESTAMP (TP_BEGINGNBPCIETRAINING, GnbLibGetHeader (Pcie));
Status = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTrainingV2 Enter\n");
do {
TrainingComplete = TRUE;
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PcieTrainingPortCallback,
&TrainingComplete,
Pcie
);
} while (!TrainingComplete);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieTrainingV2 Exit [%x]\n", Status);
IDS_PERF_TIMESTAMP (TP_ENDGNBPCIETRAINING, GnbLibGetHeader (Pcie));
return Status;
}
/**
* Build integrated info table
*
*
*
* @param[in] Gfx Gfx configuration info
* @param[in] SystemInfoTableV3 ATOM_FUSION_SYSTEM_INFO_V3 pointer
* @param[in] PpF1Array
* @retval AGESA_STATUS
*/
AGESA_STATUS
GfxIntInfoTableInitV3 (
IN GFX_PLATFORM_CONFIG *Gfx,
IN ATOM_FUSION_SYSTEM_INFO_V3 *SystemInfoTableV3,
IN PP_F1_ARRAY_V2 *PpF1Array
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
PCIe_PLATFORM_CONFIG *Pcie;
ATOM_PPLIB_POWERPLAYTABLE4 *PpTable;
UINT8 Channel;
AgesaStatus = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInitV3 Enter\n");
if (PpF1Array != NULL) {
Channel = 0;
if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT1) != 0) {
Channel = 1;
} else if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT2) != 0) {
Channel = 2;
} else if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT3) != 0) {
Channel = 3;
}
SystemInfoTableV3->sIntegratedSysInfo.sHeader.usStructureSize = sizeof (ATOM_INTEGRATED_SYSTEM_INFO_V1_8);
ASSERT (SystemInfoTableV3->sIntegratedSysInfo.sHeader.usStructureSize == 512);
SystemInfoTableV3->sIntegratedSysInfo.sHeader.ucTableFormatRevision = 1;
SystemInfoTableV3->sIntegratedSysInfo.sHeader.ucTableContentRevision = 8;
SystemInfoTableV3->sIntegratedSysInfo.ulBootUpEngineClock = 200 * 100; //Set default engine clock to 200MhZ
SystemInfoTableV3->sIntegratedSysInfo.field2 = (PpF1Array->PP_FUSE_ARRAY_V2_fld21 + 0x10) * 10000;
SystemInfoTableV3->sIntegratedSysInfo.ulBootUpUMAClock = Gfx->UmaInfo.MemClock * 100;
SystemInfoTableV3->sIntegratedSysInfo.usRequestedPWMFreqInHz = Gfx->LcdBackLightControl;
SystemInfoTableV3->sIntegratedSysInfo.ucUMAChannelNumber = ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_INTERLEAVE) == 0) ? 1 : 2;
SystemInfoTableV3->sIntegratedSysInfo.ucMemoryType = Gfx->UmaInfo.MemType;
SystemInfoTableV3->sIntegratedSysInfo.usBootUpNBVoltage = GnbLocateHighestVidIndexV5 (GnbLibGetHeader (Gfx));
SystemInfoTableV3->sIntegratedSysInfo.usPanelRefreshRateRange = Gfx->DynamicRefreshRate;
SystemInfoTableV3->sIntegratedSysInfo.usLvdsSSPercentage = Gfx->LvdsSpreadSpectrum;
//Locate PCIe configuration data to get definitions of display connectors
SystemInfoTableV3->sIntegratedSysInfo.sExtDispConnInfo.sHeader.usStructureSize = sizeof (ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO);
SystemInfoTableV3->sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableFormatRevision = 1;
SystemInfoTableV3->sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableContentRevision = 1;
SystemInfoTableV3->sIntegratedSysInfo.sExtDispConnInfo.uc3DStereoPinId = Gfx->Gnb3dStereoPinIndex;
SystemInfoTableV3->sIntegratedSysInfo.sExtDispConnInfo.ucRemoteDisplayConfig = Gfx->GnbRemoteDisplaySupport;
SystemInfoTableV3->sIntegratedSysInfo.sExtDispConnInfo.ucFixDPVoltageSwing = (UINT8) Gfx->DpFixedVoltSwingType;
SystemInfoTableV3->sIntegratedSysInfo.usExtDispConnInfoOffset = offsetof (ATOM_INTEGRATED_SYSTEM_INFO_V1_8, sExtDispConnInfo);
SystemInfoTableV3->sIntegratedSysInfo.usPCIEClkSSPercentage = Gfx->PcieRefClkSpreadSpectrum;
SystemInfoTableV3->sIntegratedSysInfo.ucLvdsMisc = Gfx->LvdsMiscControl.Value;
IDS_HDT_CONSOLE (GNB_TRACE, "Lvds Misc control : %x\n", Gfx->LvdsMiscControl.Value);
if (Gfx->LvdsMiscControl.Field.LvdsVoltOverwriteEn) {
SystemInfoTableV3->sIntegratedSysInfo.ucLVDSVoltAdjust = Gfx->LVDSVoltAdjust;
IDS_HDT_CONSOLE (GNB_TRACE, "LVDSVoltAdjust : %x\n", Gfx->LVDSVoltAdjust);
}
SystemInfoTableV3->sIntegratedSysInfo.ulVBIOSMisc = Gfx->DisplayMiscControl.Value;
IDS_HDT_CONSOLE (GNB_TRACE, "Display Misc control : %x\n", Gfx->DisplayMiscControl.Value);
// LVDS
SystemInfoTableV3->sIntegratedSysInfo.ucLVDSPwrOnSeqDIGONtoDE_in4Ms = Gfx->LvdsPowerOnSeqDigonToDe;
SystemInfoTableV3->sIntegratedSysInfo.ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms = Gfx->LvdsPowerOnSeqDeToVaryBl;
SystemInfoTableV3->sIntegratedSysInfo.ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms = Gfx->LvdsPowerOnSeqVaryBlToDe;
SystemInfoTableV3->sIntegratedSysInfo.ucLVDSPwrOffSeqDEtoDIGON_in4Ms = Gfx->LvdsPowerOnSeqDeToDigon;
SystemInfoTableV3->sIntegratedSysInfo.ucLVDSOffToOnDelay_in4Ms = Gfx->LvdsPowerOnSeqOnToOffDelay;
SystemInfoTableV3->sIntegratedSysInfo.ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms = Gfx->LvdsPowerOnSeqVaryBlToBlon;
SystemInfoTableV3->sIntegratedSysInfo.ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms = Gfx->LvdsPowerOnSeqBlonToVaryBl;
SystemInfoTableV3->sIntegratedSysInfo.ulLCDBitDepthControlVal = Gfx->LcdBitDepthControlValue;
SystemInfoTableV3->sIntegratedSysInfo.usMaxLVDSPclkFreqInSingleLink = Gfx->LvdsMaxPixelClockFreq;
SystemInfoTableV3->sIntegratedSysInfo.ucMinAllowedBL_Level = Gfx->MinAllowedBLLevel;
Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie);
ASSERT (Status == AGESA_SUCCESS);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_SUCCESS) {
Status = GfxIntegratedEnumerateAllConnectors (
&SystemInfoTableV3->sIntegratedSysInfo.sExtDispConnInfo.sPath[0],
Pcie,
Gfx
);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
SystemInfoTableV3->sIntegratedSysInfo.sExtDispConnInfo.uceDPToLVDSRxId = eDP_TO_LVDS_RX_DISABLE;
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE,
GfxIntegrateducEDPToLVDSRxIdCallback,
&SystemInfoTableV3->sIntegratedSysInfo.sExtDispConnInfo.uceDPToLVDSRxId,
Pcie
);
// Build PP table
PpTable = (ATOM_PPLIB_POWERPLAYTABLE4*) &SystemInfoTableV3->ulPowerplayTable;
// Build PP table
///@todo
//Status = GfxPowerPlayBuildTable (PpTable, Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
// Assign usFormatID to 0x000B to represent V3
///@todo
PpTable->usFormatID = 0xB;
// Build Display clock info
GfxIntegratedInfoTable289_fun (PpF1Array, &SystemInfoTableV3->sIntegratedSysInfo, Gfx);
GfxIntegratedInfoTable318_fun (PpF1Array, &SystemInfoTableV3->sIntegratedSysInfo, Gfx);
///@todo review if these parameters needed
// Fill in Nb P-state MemclkFreq Data
GfxFillNbPstateMemclkFreqV3 (&SystemInfoTableV3->sIntegratedSysInfo, PpF1Array, Gfx);
// Fill in HTC Data
if (PpF1Array->HtcEn == 1) {
SystemInfoTableV3->sIntegratedSysInfo.ucHtcTmpLmt = (UCHAR) (PpF1Array->HtcTmpLmt / 2 + 52);
SystemInfoTableV3->sIntegratedSysInfo.ATOM_INTEGRATED_SYSTEM_INFO_V1_8_fld11 = (UCHAR) (PpF1Array->PP_FUSE_ARRAY_V2_fld20 / 2);
} else {
SystemInfoTableV3->sIntegratedSysInfo.ucHtcTmpLmt = 0;
SystemInfoTableV3->sIntegratedSysInfo.ATOM_INTEGRATED_SYSTEM_INFO_V1_8_fld11 = 0;
}
// Fill in NB P states VID & NCLK info
GfxFillNbPStateVidV3 (PpF1Array, &SystemInfoTableV3->sIntegratedSysInfo, Gfx);
// Family specific data update - store default values to be updated by family specific code
//GfxFmIntegratedInfoTableInit (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
SystemInfoTableV3->sIntegratedSysInfo.ulDDR_DLL_PowerUpTime = 4940;
SystemInfoTableV3->sIntegratedSysInfo.ulDDR_PLL_PowerUpTime = 2000;
if (PpF1Array->MemPhyPllPdMode[Channel] != 0) {
SystemInfoTableV3->sIntegratedSysInfo.ulSystemConfig |= BIT2;
}
if (PpF1Array->DisDllShutdownSR[Channel] == 0) {
SystemInfoTableV3->sIntegratedSysInfo.ulSystemConfig |= BIT1;
}
if (GnbBuildOptions.CfgPciePowerGatingFlags != (PCIE_POWERGATING_SKIP_CORE | PCIE_POWERGATING_SKIP_PHY)) {
SystemInfoTableV3->sIntegratedSysInfo.ulSystemConfig |= BIT0;
}
SystemInfoTableV3->sIntegratedSysInfo.ulGPUCapInfo = GPUCAPINFO_TMDS_HDMI_USE_CASCADE_PLL_MODE | GPUCAPINFO_DP_USE_SINGLE_PLL_MODE;
IDS_HDT_CONSOLE (GNB_TRACE, "ulSystemConfig : %x\n", SystemInfoTableV3->sIntegratedSysInfo.ulSystemConfig);
} else {
Status = AGESA_ERROR;
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInitV3 Exit [0x%x]\n", Status);
return Status;
}
AGESA_STATUS
GnbCableSafeEntry (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
PCIe_PLATFORM_CONFIG *Pcie;
PCIe_ENGINE_CONFIG *DdiEngineList [MaxHdp];
UINT8 HdpIndex;
UINT8 CurrentIndex;
GNB_CABLE_SAFE_DATA CableSafeData;
BOOLEAN ForceCableSafeOff;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbCableSafeEntry Enter\n");
Status = AGESA_SUCCESS;
ForceCableSafeOff = GnbBuildOptions.CfgForceCableSafeOff;
IDS_OPTION_HOOK (IDS_GNB_FORCE_CABLESAFE, &ForceCableSafeOff, StdHeader);
if (GnbCableSafeIsSupported (StdHeader)) {
if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) {
for (HdpIndex = 0; HdpIndex < MaxHdp; HdpIndex++) {
DdiEngineList[HdpIndex] = NULL;
}
LibAmdMemFill (&CableSafeData, 0, sizeof (CableSafeData), StdHeader);
if (!ForceCableSafeOff) {
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_DDI_ENGINE,
GnbCableSafeGetConnectorInfoArrayCallback,
DdiEngineList,
Pcie
);
CurrentIndex = 0;
for (HdpIndex = 0; HdpIndex < MaxHdp; HdpIndex++) {
if (DdiEngineList [HdpIndex] != NULL) {
CableSafeData.Data[HdpIndexTranslationTable[CurrentIndex]] = HdpIndex + 1;
CableSafeData.Data[AuxIndexTranslationTable[CurrentIndex]] = AuxDataTranslationTable [(DdiEngineList [HdpIndex])->Type.Ddi.DdiData.AuxIndex];
IDS_HDT_CONSOLE (NB_MISC, " Index [%d] HDP 0x%02x AUX 0x%02x\n", CurrentIndex, HdpIndex, (DdiEngineList [HdpIndex])->Type.Ddi.DdiData.AuxIndex);
CurrentIndex++;
}
}
} else {
GMMx6124_STRUCT GMMx6124;
GMMx6124.Value = 0x3F;
NbSmuSrbmRegisterWrite (SMU_GMM_TO_FCR (GMMx6124_ADDRESS), &GMMx6124.Value, TRUE, GnbLibGetHeader (Pcie));
GnbLibPciRMW (
MAKE_SBDFO (0, 0, 0x18, 6, D18F6x80_ADDRESS),
AccessWidth32,
0xffffffff,
(7 << D18F6x80_CableSafeDisAux_3_1_OFFSET) | (7 << D18F6x80_CableSafeDisAux_6_4_OFFSET),
GnbLibGetHeader (Pcie)
);
}
CableSafeData.Config.Enable = 0x1;
CableSafeData.Config.DebounceFilter = 0;
CableSafeData.Config.SoftPeriod = 0x4;
CableSafeData.Config.Unit = 0x1;
CableSafeData.Config.Period = 0xf424;
NbSmuRcuRegisterWrite (
SMUx0B_x85D0_ADDRESS,
(UINT32*) &CableSafeData,
sizeof (CableSafeData) / sizeof (UINT32),
TRUE,
StdHeader
);
NbSmuServiceRequest (0x05, TRUE, StdHeader);
} else {
Status = AGESA_ERROR;
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "GnbCableSafeEntry Exit [Status = 0x%04x]\n", Status);
return Status;
}
/**
* Build integrated info table
*
*
*
* @param[in] Gfx Gfx configuration info
* @retval AGESA_STATUS
*/
AGESA_STATUS
STATIC
GfxIntInfoTableInitTN (
IN GFX_PLATFORM_CONFIG *Gfx
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
ATOM_FUSION_SYSTEM_INFO_V2 SystemInfoTableV2;
PP_FUSE_ARRAY *PpFuseArray;
PCIe_PLATFORM_CONFIG *Pcie;
ATOM_PPLIB_POWERPLAYTABLE3 *PpTable;
UINT8 Channel;
AgesaStatus = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInitTN Enter\n");
LibAmdMemFill (&SystemInfoTableV2, 0x00, sizeof (ATOM_FUSION_SYSTEM_INFO_V2), GnbLibGetHeader (Gfx));
SystemInfoTableV2.sIntegratedSysInfo.sHeader.usStructureSize = sizeof (ATOM_INTEGRATED_SYSTEM_INFO_V1_7);
ASSERT (SystemInfoTableV2.sIntegratedSysInfo.sHeader.usStructureSize == 512);
SystemInfoTableV2.sIntegratedSysInfo.sHeader.ucTableFormatRevision = 1;
SystemInfoTableV2.sIntegratedSysInfo.sHeader.ucTableContentRevision = 7;
SystemInfoTableV2.sIntegratedSysInfo.ulDentistVCOFreq = GfxLibGetSytemPllCofTN (GnbLibGetHeader (Gfx)) * 100;
SystemInfoTableV2.sIntegratedSysInfo.ulBootUpUMAClock = Gfx->UmaInfo.MemClock * 100;
SystemInfoTableV2.sIntegratedSysInfo.usRequestedPWMFreqInHz = Gfx->LcdBackLightControl;
SystemInfoTableV2.sIntegratedSysInfo.ucUMAChannelNumber = ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_INTERLEAVE) == 0) ? 1 : 2;
SystemInfoTableV2.sIntegratedSysInfo.ucMemoryType = 3; //DDR3
SystemInfoTableV2.sIntegratedSysInfo.ulBootUpEngineClock = 200 * 100; //Set default engine clock to 200MhZ
SystemInfoTableV2.sIntegratedSysInfo.usBootUpNBVoltage = GnbLocateHighestVidIndex (GnbLibGetHeader (Gfx));
SystemInfoTableV2.sIntegratedSysInfo.ulMinEngineClock = 200 * 100;
SystemInfoTableV2.sIntegratedSysInfo.usPanelRefreshRateRange = Gfx->DynamicRefreshRate;
SystemInfoTableV2.sIntegratedSysInfo.usLvdsSSPercentage = Gfx->LvdsSpreadSpectrum;
//Locate PCIe configuration data to get definitions of display connectors
SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.usStructureSize = sizeof (ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO);
SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableFormatRevision = 1;
SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableContentRevision = 1;
SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uc3DStereoPinId = Gfx->Gnb3dStereoPinIndex;
SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.ucRemoteDisplayConfig = Gfx->GnbRemoteDisplaySupport;
SystemInfoTableV2.sIntegratedSysInfo.usExtDispConnInfoOffset = offsetof (ATOM_INTEGRATED_SYSTEM_INFO_V1_7, sExtDispConnInfo);
SystemInfoTableV2.sIntegratedSysInfo.ulSB_MMIO_Base_Addr = SbGetSbMmioBaseAddress (GnbLibGetHeader (Gfx));
SystemInfoTableV2.sIntegratedSysInfo.usPCIEClkSSPercentage = Gfx->PcieRefClkSpreadSpectrum;
SystemInfoTableV2.sIntegratedSysInfo.ucLvdsMisc = Gfx->LvdsMiscControl.Value;
IDS_HDT_CONSOLE (GNB_TRACE, "Lvds Misc control : %x\n", Gfx->LvdsMiscControl.Value);
if (Gfx->LvdsMiscControl.Field.TravisLvdsVoltOverwriteEn) {
SystemInfoTableV2.sIntegratedSysInfo.gnbgfxline429 = Gfx->gfxplmcfg0 ;
IDS_HDT_CONSOLE (GNB_TRACE, "TravisLVDSVoltAdjust : %x\n", Gfx->gfxplmcfg0 );
}
SystemInfoTableV2.sIntegratedSysInfo.ulOtherDisplayMisc = Gfx->DisplayMiscControl.Value;
IDS_HDT_CONSOLE (GNB_TRACE, "Display Misc control : %x\n", Gfx->DisplayMiscControl.Value);
// LVDS
SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqDIGONtoDE_in4Ms = Gfx->LvdsPowerOnSeqDigonToDe;
SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms = Gfx->LvdsPowerOnSeqDeToVaryBl;
SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms = Gfx->LvdsPowerOnSeqVaryBlToDe;
SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqDEtoDIGON_in4Ms = Gfx->LvdsPowerOnSeqDeToDigon;
SystemInfoTableV2.sIntegratedSysInfo.ucLVDSOffToOnDelay_in4Ms = Gfx->LvdsPowerOnSeqOnToOffDelay;
SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms = Gfx->LvdsPowerOnSeqVaryBlToBlon;
SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms = Gfx->LvdsPowerOnSeqBlonToVaryBl;
SystemInfoTableV2.sIntegratedSysInfo.ulLCDBitDepthControlVal = Gfx->LcdBitDepthControlValue;
SystemInfoTableV2.sIntegratedSysInfo.usMaxLVDSPclkFreqInSingleLink = Gfx->LvdsMaxPixelClockFreq;
Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie);
ASSERT (Status == AGESA_SUCCESS);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_SUCCESS) {
Status = GfxIntegratedEnumerateAllConnectors (
&SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sPath[0],
Pcie,
Gfx
);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uceDPToLVDSRxId = eDP_TO_LVDS_RX_DISABLE;
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE,
GfxIntegrateducEDPToLVDSRxIdCallback,
&SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uceDPToLVDSRxId,
Pcie
);
// Build PP table
PpTable = (ATOM_PPLIB_POWERPLAYTABLE3*) &SystemInfoTableV2.ulPowerplayTable;
// Build PP table
Status = GfxPowerPlayBuildTable (PpTable, Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
// Assign usFormatID to 0x000B to represent Trinity
PpTable->usFormatID = 0xB;
// Build info from fuses
PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx));
ASSERT (PpFuseArray != NULL);
if (PpFuseArray != NULL) {
// Build Display clock info
GfxIntInfoTableInitDispclkTable (PpFuseArray, &SystemInfoTableV2.sIntegratedSysInfo, Gfx);
// Build Sclk info table
GfxIntInfoTableInitSclkTable (PpFuseArray, &SystemInfoTableV2.sIntegratedSysInfo, Gfx);
} else {
Status = AGESA_ERROR;
AGESA_STATUS_UPDATE (Status, AgesaStatus);
}
//@todo review if thouse parameters needed
// Fill in Nb P-state MemclkFreq Data
GfxFillNbPstateMemclkFreqTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx);
// Fill in HTC Data
GfxFillHtcDataTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx);
// Fill in NB P states VID
GfxFillNbPStateVidTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx);
// Fill in NCLK info
//GfxFillNclkInfo (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
// Fill in the M3 arbitration control tables
//GfxFillM3ArbritrationControl (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
// Family specific data update
// Determine ulGMCRestoreResetTime
Status = GfxCalculateRestoreResetTimeTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx, PpFuseArray);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
//GfxFmIntegratedInfoTableInit (&SystemInfoV1Table.sIntegratedSysInfo, Gfx);
SystemInfoTableV2.sIntegratedSysInfo.ulDDR_DLL_PowerUpTime = 4940;
SystemInfoTableV2.sIntegratedSysInfo.ulDDR_PLL_PowerUpTime = 2000;
if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT0) != 0) {
Channel = 0;
} else {
Channel = 1;
}
if (GfxLibGetMemPhyPllPdModeTN (Channel, GnbLibGetHeader (Gfx)) != 0) {
SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT2;
}
if (GfxLibGetDisDllShutdownSRTN (Channel, GnbLibGetHeader (Gfx)) == 0) {
SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT1;
}
if (GnbBuildOptions.CfgPciePowerGatingFlags != (PCIE_POWERGATING_SKIP_CORE | PCIE_POWERGATING_SKIP_PHY)) {
SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT0;
}
SystemInfoTableV2.sIntegratedSysInfo.ulGPUCapInfo = GPUCAPINFO_TMDS_HDMI_USE_CASCADE_PLL_MODE | GPUCAPINFO_DP_USE_SINGLE_PLL_MODE;
IDS_HDT_CONSOLE (GNB_TRACE, "ulSystemConfig : %x\n", SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig);
IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG, &SystemInfoTableV2.sIntegratedSysInfo, GnbLibGetHeader (Gfx));
//Copy integrated info table to Frame Buffer. (Do not use LibAmdMemCopy, routine not guaranteed access to above 4G memory in 32 bit mode.)
GfxIntInfoTabablePostToFb (&SystemInfoTableV2, Gfx);
IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInit Exit [0x%x]\n", Status);
return Status;
}
/**
* Enumerate all display connectors for specific display device type.
*
*
*
* @param[in] DisplayDeviceEnum Display device list
* @param[out] DisplayPathList Display path list
* @param[in,out] Pcie PCIe configuration info
* @param[in] Gfx Gfx configuration info
*/
AGESA_STATUS
GfxIntegratedEnumConnectorsForDevice (
IN UINT8 DisplayDeviceEnum,
OUT EXT_DISPLAY_PATH *DisplayPathList,
IN OUT PCIe_PLATFORM_CONFIG *Pcie,
IN GFX_PLATFORM_CONFIG *Gfx
)
{
UINT8 DisplayDeviceIndex;
CONNECTOR_ENUM_INFO ConnectorEnumInfo;
EXT_CONNECTOR_INFO *ExtConnectorInfo;
EXT_DISPLAY_DEVICE_INFO *ExtDisplayDeviceInfo;
AGESA_STATUS Status;
UINT8 ConnectorIdArray[sizeof (ConnectorNumerArray)];
ConnectorEnumInfo.Status = AGESA_SUCCESS;
DisplayDeviceIndex = 1;
ConnectorEnumInfo.RequestedPriorityIndex = 0;
ConnectorEnumInfo.DisplayDeviceEnum = DisplayDeviceEnum;
LibAmdMemFill (ConnectorIdArray, 0x00, sizeof (ConnectorIdArray), GnbLibGetHeader (Gfx));
do {
ConnectorEnumInfo.Engine = NULL;
ConnectorEnumInfo.CurrentPriorityIndex = 0xff;
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE,
GfxIntegratedDdiInterfaceCallback,
&ConnectorEnumInfo,
Pcie
);
if (ConnectorEnumInfo.Engine == NULL) {
break; // No more connector support this
}
ConnectorEnumInfo.RequestedPriorityIndex = ConnectorEnumInfo.CurrentPriorityIndex + 1;
ExtConnectorInfo = GfxIntegratedExtConnectorInfo (ConnectorEnumInfo.Engine->Type.Ddi.DdiData.ConnectorType);
ASSERT (ExtConnectorInfo != NULL);
ASSERT (ExtConnectorInfo->ConnectorIndex < sizeof (ConnectorIdArray));
if (ConnectorIdArray[ExtConnectorInfo->ConnectorIndex] >= ConnectorNumerArray[ExtConnectorInfo->ConnectorIndex]) {
//Run out of supported connectors
AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status);
PcieConfigDisableEngine (ConnectorEnumInfo.Engine);
continue;
}
ConnectorEnumInfo.Engine->Type.Ddi.ConnectorId = ConnectorIdArray[ExtConnectorInfo->ConnectorIndex] + 1;
ExtDisplayDeviceInfo = GfxIntegratedExtDisplayDeviceInfo (DisplayDeviceEnum, DisplayDeviceIndex);
if (ExtDisplayDeviceInfo == NULL) {
//Run out of supported display device types
AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status);
Status = AGESA_ERROR;
PcieConfigDisableEngine (ConnectorEnumInfo.Engine);
}
if ((Gfx->Gnb3dStereoPinIndex != 0) && (ConnectorEnumInfo.Engine->Type.Ddi.DdiData.HdpIndex == (Gfx->Gnb3dStereoPinIndex - 1))) {
AGESA_STATUS_UPDATE (AGESA_ERROR, ConnectorEnumInfo.Status);
Status = AGESA_ERROR;
PcieConfigDisableEngine (ConnectorEnumInfo.Engine);
}
ConnectorEnumInfo.Engine->Type.Ddi.DisplayDeviceId = DisplayDeviceIndex;
Status = GfxFmMapEngineToDisplayPath (ConnectorEnumInfo.Engine, DisplayPathList, Gfx);
AGESA_STATUS_UPDATE (Status, ConnectorEnumInfo.Status);
if (Status != AGESA_SUCCESS) {
continue;
}
ConnectorIdArray[ExtConnectorInfo->ConnectorIndex]++;
DisplayDeviceIndex++;
} while (ConnectorEnumInfo.Engine != NULL);
return ConnectorEnumInfo.Status;
}
AGESA_STATUS
PcieAlibBuildAcpiTable (
IN AMD_CONFIG_PARAMS *StdHeader,
OUT VOID **AlibSsdtPtr
)
{
AGESA_STATUS Status;
UINT32 AmlObjName;
PCIe_PLATFORM_CONFIG *Pcie;
PP_FUSE_ARRAY *PpFuseArray;
VOID *AlibSsdtBuffer;
VOID *AmlObjPtr;
UINT8 SclkVidArray[4];
UINT8 BootUpVid;
UINT8 BootUpVidIndex;
UINT8 Gen1VidIndex;
UINTN Index;
UINTN AlibSsdtlength;
Status = AGESA_SUCCESS;
AlibSsdtlength = ((ACPI_TABLE_HEADER*) &AlibSsdt[0])->TableLength;
if (*AlibSsdtPtr == NULL) {
AlibSsdtBuffer = GnbAllocateHeapBuffer (
AMD_ACPI_ALIB_BUFFER_HANDLE,
AlibSsdtlength,
StdHeader
);
ASSERT (AlibSsdtBuffer != NULL);
if (AlibSsdtBuffer == NULL) {
return AGESA_ERROR;
}
*AlibSsdtPtr = AlibSsdtBuffer;
} else {
AlibSsdtBuffer = *AlibSsdtPtr;
}
// Copy template to buffer
LibAmdMemCopy (AlibSsdtBuffer, &AlibSsdt[0], AlibSsdtlength, StdHeader);
// Set PCI MMIO configuration
// AmlObjName = '10DA';
AmlObjName = Int32FromChar ('A', 'D', '0', '1');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
if (AmlObjPtr != NULL) {
UINT64 MsrReg;
LibAmdMsrRead (MSR_MMIO_Cfg_Base, &MsrReg, StdHeader);
if ((MsrReg & BIT0) != 0 && (MsrReg & 0xFFFFFFFF00000000) == 0) {
*(UINT32*)((UINT8*)AmlObjPtr + 5) = (UINT32)(MsrReg & 0xFFFFF00000);
} else {
Status = AGESA_ERROR;
}
} else {
Status = AGESA_ERROR;
}
// Set voltage configuration
PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader);
if (PpFuseArray != NULL) {
// AmlObjName = '30DA';
AmlObjName = Int32FromChar ('A', 'D', '0', '3');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
*(UINT8*)((UINT8*)AmlObjPtr + 5) = PpFuseArray->PcieGen2Vid;
} else {
Status = AGESA_ERROR;
}
} else {
Status = AGESA_ERROR;
}
GnbLibPciRead (
MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS),
AccessWidth32,
&SclkVidArray[0],
StdHeader
);
Gen1VidIndex = 0;
BootUpVidIndex = 0;
BootUpVid = 0xff;
for (Index = 0; Index < 4; Index++) {
if (SclkVidArray[Index] > SclkVidArray[Gen1VidIndex]) {
Gen1VidIndex = (UINT8) Index;
}
if (SclkVidArray[Index] != 0 && SclkVidArray[Index] < BootUpVid) {
BootUpVid = SclkVidArray[Index];
BootUpVidIndex = (UINT8) Index;
}
}
// AmlObjName = '40DA';
AmlObjName = Int32FromChar ('A', 'D', '0', '4');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
*(UINT8*)((UINT8*)AmlObjPtr + 5) = Gen1VidIndex;
} else {
Status = AGESA_ERROR;
}
// AmlObjName = '50DA';
AmlObjName = Int32FromChar ('A', 'D', '0', '5');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
*(UINT8*)((UINT8*)AmlObjPtr + 5) = BootUpVidIndex;
} else {
Status = AGESA_ERROR;
}
// Set PCIe configuration
if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) {
// AmlObjName = '20DA';
AmlObjName = Int32FromChar ('A', 'D', '0', '2');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
*(UINT8*)((UINT8*)AmlObjPtr + 5) = Pcie->PsppPolicy;
} else {
Status = AGESA_ERROR;
}
// AmlObjName = '60DA';
AmlObjName = Int32FromChar ('A', 'D', '0', '6');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PcieAlibSetPortMaxSpeedCallback,
(UINT8*)((UINT8*)AmlObjPtr + 7),
Pcie
);
} else {
Status = AGESA_ERROR;
}
// AmlObjName = '80DA';
AmlObjName = Int32FromChar ('A', 'D', '0', '8');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PcieAlibSetPortOverrideSpeedCallback,
(UINT8*)((UINT8*)AmlObjPtr + 7),
Pcie
);
} else {
Status = AGESA_ERROR;
}
// AmlObjName = '70DA';
AmlObjName = Int32FromChar ('A', 'D', '0', '7');
AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName));
ASSERT (AmlObjPtr != NULL);
if (AmlObjPtr != NULL) {
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PcieAlibSetPortInfoCallback,
(UINT8*)((UINT8*)AmlObjPtr + 4),
Pcie
);
} else {
Status = AGESA_ERROR;
}
} else {
ASSERT (FALSE);
Status = AGESA_ERROR;
}
if (Status == AGESA_SUCCESS) {
Status = PcieFmAlibBuildAcpiTable (AlibSsdtBuffer, StdHeader);
}
if (Status != AGESA_SUCCESS) {
//Shrink table length to size of the header
((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength = sizeof (ACPI_TABLE_HEADER);
}
ChecksumAcpiTable ((ACPI_TABLE_HEADER*) AlibSsdtBuffer, StdHeader);
return Status;
}