CMPBR_INST ("cmpbhid", 0xA, 0xE, 0x4),
CMPBR_INST ("cmpblsd", 0xA, 0xE, 0x5),
CMPBR_INST ("cmpbgtd", 0xA, 0xE, 0x6),
CMPBR_INST ("cmpbled", 0xA, 0xE, 0x7),
CMPBR_INST ("cmpblod", 0xA, 0xE, 0xA),
CMPBR_INST ("cmpbhsd", 0xA, 0xE, 0xB),
CMPBR_INST ("cmpbltd", 0xA, 0xE, 0xC),
CMPBR_INST ("cmpbged", 0xA, 0xE, 0xD),
/* Create an instruction using a single register operand. */
#define REG1_INST(NAME, OPC) \
/* opc8 c4 r */ \
{NAME, 1, OPC, 20, 0, {{regr,16}}}
/* JCond instructions */
REG1_INST ("jeq", 0xBA0),
REG1_INST ("jne", 0xBA1),
REG1_INST ("jcs", 0xBA2),
REG1_INST ("jcc", 0xBA3),
REG1_INST ("jhi", 0xBA4),
REG1_INST ("jls", 0xBA5),
REG1_INST ("jgt", 0xBA6),
REG1_INST ("jle", 0xBA7),
REG1_INST ("jfs", 0xBA8),
REG1_INST ("jfc", 0xBA9),
REG1_INST ("jlo", 0xBAA),
REG1_INST ("jhs", 0xBAB),
REG1_INST ("jlt", 0xBAC),
REG1_INST ("jge", 0xBAD),
REG1_INST ("jump", 0xBAE),
REGP1_INST ("jcc", 0x0A3),
REGP1_INST ("jhi", 0x0A4),
REGP1_INST ("jls", 0x0A5),
REGP1_INST ("jgt", 0x0A6),
REGP1_INST ("jle", 0x0A7),
REGP1_INST ("jfs", 0x0A8),
REGP1_INST ("jfc", 0x0A9),
REGP1_INST ("jlo", 0x0AA),
REGP1_INST ("jhs", 0x0AB),
REGP1_INST ("jlt", 0x0AC),
REGP1_INST ("jge", 0x0AD),
REGP1_INST ("jump", 0x0AE),
REGP1_INST ("jusr", 0x0AF),
/* SCond instructions */
REG1_INST ("seq", 0x080),
REG1_INST ("sne", 0x081),
REG1_INST ("scs", 0x082),
REG1_INST ("scc", 0x083),
REG1_INST ("shi", 0x084),
REG1_INST ("sls", 0x085),
REG1_INST ("sgt", 0x086),
REG1_INST ("sle", 0x087),
REG1_INST ("sfs", 0x088),
REG1_INST ("sfc", 0x089),
REG1_INST ("slo", 0x08A),
REG1_INST ("shs", 0x08B),
REG1_INST ("slt", 0x08C),
REG1_INST ("sge", 0x08D),
