{NAME, 2, OPC, 12, NO_TYPE_INS, {{regp,0}, {regp,4}}}
/* Jump and link instructions. */
REGP1_INST ("jal",0x00D),
REGPP2_INST ("jal",0x00148),
/* Instructions including a register list (opcode is represented as a mask). */
#define REGLIST_INST(NAME, OPC, TYPE) \
/* opc7 r count3 RA */ \
{NAME,1, (OPC<<1)+1, 23, TYPE, {{uimm3_1,20},{regr,16},{regr,0}}}, \
/* opc8 r count3 */ \
{NAME, 1, OPC, 24, TYPE, {{uimm3_1,20}, {regr,16}}}, \
/* opc12 RA */ \
{NAME, 1, (OPC<<8)+0x1E, 16, TYPE, {{regr,0}}}
REGLIST_INST ("push", 0x01, (NO_TYPE_INS | REG_LIST)),
REGLIST_INST ("pop", 0x02, (NO_TYPE_INS | REG_LIST)),
REGLIST_INST ("popret", 0x03, (NO_TYPE_INS | REG_LIST)),
{"loadm", 1, 0x14, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}},
{"loadmp", 1, 0x15, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}},
{"storm", 1, 0x16, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}},
{"stormp", 1, 0x17, 19, NO_TYPE_INS | REG_LIST, {{uimm3_1,16}}},
/* Processor Regsiter Manipulation instructions */
/* opc16 reg, preg */
{"lpr", 2, 0x00140, 12, NO_TYPE_INS, {{regr,0}, {pregr,4}}},
/* opc16 regp, pregp */
{"lprd", 2, 0x00141, 12, NO_TYPE_INS, {{regp,0}, {pregrp,4}}},
/* opc16 preg, reg */
{"spr", 2, 0x00142, 12, NO_TYPE_INS, {{pregr,4}, {regr,0}}},
CSTBIT_INST ("tbitb", i3, 0x702, 0x20, 19, 0x1FE),
CSTBIT_INST ("tbitw", i4, 0x384, 0x10, 20, 0xBF),
CSTBIT_INST ("tbitd", i5, 0x1C5, 0x8, 21, 0x7D),
{"tbitd", 2, 0x30083A, 8, CSTBIT_INS, {{regr,4}, {regr,0}}},
{"tbitd", 2, 0x18047D, 9, CSTBIT_INS, {{i5,4}, {regr,0}}},
/* Instructions including a register list (opcode is represented as a mask). */
#define REGLIST_INST(NAME, OPC) \
/* opc12 r mask16 */ \
{NAME, 2, OPC, 20, REG_LIST, {{regr,16}, {i16,0}}}
REG1_INST ("getrfid", 0xFF9),
REG1_INST ("setrfid", 0xFFA),
REGLIST_INST ("push", 0x346),
REG1_INST ("push", 0xFFB),
REGLIST_INST ("pushx", 0x347),
REGLIST_INST ("pop", 0x324),
REG1_INST ("pop", 0xFFC),
REGLIST_INST ("popx", 0x327),
REGLIST_INST ("popret", 0x326),
REG1_INST ("popret", 0xFFD),
REGLIST_INST ("loadm", 0x324),
REGLIST_INST ("loadma", 0x325),
REGLIST_INST ("popa", 0x325),
REGLIST_INST ("storm", 0x344),
CSTBIT_INST ("tbitb", ui3, 0x702, 0x20, 19, 0x1FE),
CSTBIT_INST ("tbitw", ui4, 0x384, 0x10, 20, 0xBF),
CSTBIT_INST ("tbitd", ui5, 0x1C5, 0x8, 21, 0x7D),
{"tbitd", 2, 0x30083A, 8, CSTBIT_INS, {{regr,4}, {regr,0}}},
{"tbitd", 2, 0x18047D, 9, CSTBIT_INS, {{ui5,4}, {regr,0}}},
/* Instructions including a register list (opcode is represented as a mask). */
#define REGLIST_INST(NAME, OPC, FLAG) \
/* opc12 r mask16 */ \
{NAME, 2, OPC, 20, NO_TYPE_INS | REG_LIST | FLAG, {{regr,16}, {ui16,0}}}
REG1_INST ("getrfid", 0xFF9),
REG1_INST ("setrfid", 0xFFA),
REGLIST_INST ("push", 0x346, NO_RPTR),
REG1_FLAG_INST ("push", 0xFFB, NO_SP),
REGLIST_INST ("pushx", 0x347, NO_RPTR),
REGLIST_INST ("pop", 0x324, NO_RPTR),
REG1_FLAG_INST ("pop", 0xFFC, NO_SP),
REGLIST_INST ("popx", 0x327, NO_RPTR),
REGLIST_INST ("popret", 0x326, NO_RPTR),
REG1_FLAG_INST ("popret",0xFFD,NO_SP),
REGLIST_INST ("loadm", 0x324, NO_RPTR),
REGLIST_INST ("loadma", 0x325, USER_REG),
REGLIST_INST ("storm", 0x344, NO_RPTR),
REGLIST_INST ("storma", 0x345, USER_REG),