void memcpy(void *target, const void *source, size_t len)
{
int ch = DMA_CHANNEL;
unsigned char *dp;
if(len < 4)
_memcpy(target, source, len);
if(((unsigned int)source < 0xa0000000) && len)
dma_cache_wback_inv((unsigned long)source, len);
if(((unsigned int)target < 0xa0000000) && len)
dma_cache_wback_inv((unsigned long)target, len);
REG_DMAC_DSAR(ch) = PHYSADDR((unsigned long)source);
REG_DMAC_DTAR(ch) = PHYSADDR((unsigned long)target);
REG_DMAC_DTCR(ch) = len / 4;
REG_DMAC_DRSR(ch) = DMAC_DRSR_RS_AUTO;
REG_DMAC_DCMD(ch) = DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | DMAC_DCMD_DS_32BIT;
REG_DMAC_DCCSR(ch) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
while (REG_DMAC_DTCR(ch));
if(len % 4)
{
dp = (unsigned char*)((unsigned int)target + (len & (4 - 1)));
for(i = 0; i < (len % 4); i++)
*dp++ = *source;
}
}
int dma_request(int ch, void (*irq_handler)(unsigned int), unsigned int arg,
unsigned int mode, unsigned int type)
{
if (!inited) {
inited = 1;
unsigned int i;
for(i= 0; i < NUM_DMA; i++)
{
dma_used[i] = 0; //Initial to not used
dma_irq[i] = 0;
}
__cpm_start_dmac();
__dmac_enable_module();
}
if(dma_used[ch]) return -1;
dma_used[ch] = 1;
dma_unit_size[ch] = UNIT_SIZE[((mode & DMAC_DCMD_DS_MASK) >> DMAC_DCMD_DS_BIT)];
REG_DMAC_DCKE |= DMAC_DCKE_CHN_ON(ch);
REG_DMAC_DCCSR(ch) = 0;
REG_DMAC_DRSR(ch) = type;
REG_DMAC_DCMD(ch) = mode;
if (irq_handler) {
request_irq(IRQ_DMA_0 + ch, irq_handler, arg);
dma_irq[ch] = 1;
}
else
dma_irq[ch] = 0;
return 0;
}
void memset16(void *target, unsigned short c, size_t len)
{
int ch = DMA_CHANNEL;
unsigned short d;
unsigned short *dp;
if(len < 32)
_memset16(target,c,len);
else
{
if(((unsigned int)target < 0xa0000000) && len)
dma_cache_wback_inv((unsigned long)target, len);
d = c;
REG_DMAC_DSAR(ch) = PHYSADDR((unsigned long)&d);
REG_DMAC_DTAR(ch) = PHYSADDR((unsigned long)target);
REG_DMAC_DTCR(ch) = len / 32;
REG_DMAC_DRSR(ch) = DMAC_DRSR_RS_AUTO;
REG_DMAC_DCMD(ch) = DMAC_DCMD_DAI | DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 | DMAC_DCMD_DS_32BYTE;
REG_DMAC_DCCSR(ch) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
while (REG_DMAC_DTCR(ch));
if(len % 32)
{
dp = (unsigned short *)((unsigned int)target + (len & (32 - 1)));
for(d = 0; d < (len % 32); d++)
*dp++ = c;
}
}
}
void dma_start(int ch, unsigned int srcAddr, unsigned int dstAddr,
unsigned int count)
{
// printf("dma gao start1\n");
dma_stop(ch);
//set_dma_addr
REG_DMAC_DSAR(ch) = srcAddr;
REG_DMAC_DDAR(ch) = dstAddr;
//set_dma_count
REG_DMAC_DTCR(ch) = count / dma_unit_size[ch];
//enable_dma
REG_DMAC_DCMD(ch) = dma_mode[ch];
REG_DMAC_DCCSR(ch) &= ~(DMAC_DCCSR_HLT|DMAC_DCCSR_TC|DMAC_DCCSR_AR);
REG_DMAC_DCCSR(ch) |= DMAC_DCCSR_NDES; /* No-descriptor transfer */
__dmac_enable_channel(ch);
if (dma_irq[ch])
__dmac_channel_enable_irq(ch);
}
void init_perihery()
{
int i;
//Initial DMA
REG_DMAC_DMACR = 0; //Global DMA disable
REG_DMAC_DMAIPR = 0; //Clear DMA interrupt pending
for(i= 0; i < MAX_DMA_NUM; i++) {
REG_DMAC_DCCSR(i) = 0; //Disable DMA channel
}
}
void dma_stop(int ch)
{
int i;
if(0 == dma_used[ch])
return;
REG_DMAC_DCCSR(ch) = 0;
if (dma_irq[ch])
__dmac_channel_disable_irq(ch);
REG_DMAC_DCKE &= ~DMAC_DCKE_CHN_ON(ch); //Close clock to this channel
dma_used[ch] = 0;
dma_irq[ch] = 0;
}
void dma_start(int ch, unsigned int srcAddr, unsigned int dstAddr,
unsigned int count)
{
//set_dma_addr
REG_DMAC_DSAR(ch) = PHYSADDR(srcAddr);
REG_DMAC_DDAR(ch) = PHYSADDR(dstAddr);
//set_dma_count
REG_DMAC_DTCR(ch) = count / dma_unit_size[ch];
//enable_dma
REG_DMAC_DCCSR(ch) |= DMAC_DCCSR_NDES; /* No-descriptor transfer */
__dmac_enable_channel(ch);
if (dma_irq[ch])
__dmac_channel_enable_irq(ch);
}
static void lb_memcpy(void *target,void* source,unsigned int len)
{
int ch = DMA_CHANNEL;
if(((unsigned int)source < 0xa0000000) && len)
dma_cache_wback_inv((unsigned long)source, len);
if(((unsigned int)target < 0xa0000000) && len)
dma_cache_wback_inv((unsigned long)target, len);
REG_DMAC_DSAR(ch) = PHYSADDR((unsigned long)source);
REG_DMAC_DTAR(ch) = PHYSADDR((unsigned long)target);
REG_DMAC_DTCR(ch) = len / 32;
REG_DMAC_DRSR(ch) = DMAC_DRSR_RS_AUTO;
REG_DMAC_DCMD(ch) = DMAC_DCMD_SAI| DMAC_DCMD_DAI | DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32|DMAC_DCMD_DS_32BYTE;
REG_DMAC_DCCSR(ch) = DMAC_DCCSR_EN | DMAC_DCCSR_NDES;
while ( REG_DMAC_DTCR(ch) );
}
void dump_jz_dma_channel(unsigned int dmanr)
{
struct dma_chan *chan;
if (dmanr > MAX_DMA_NUM)
return;
printf("DMA%d Registers:\n", dmanr);
printf(" DMACR = 0x%08x\n", REG_DMAC_DMACR);
printf(" DSAR = 0x%08x\n", REG_DMAC_DSAR(dmanr));
printf(" DTAR = 0x%08x\n", REG_DMAC_DTAR(dmanr));
printf(" DTCR = 0x%08x\n", REG_DMAC_DTCR(dmanr));
printf(" DRSR = 0x%08x\n", REG_DMAC_DRSR(dmanr));
printf(" DCCSR = 0x%08x\n", REG_DMAC_DCCSR(dmanr));
printf(" DCMD = 0x%08x\n", REG_DMAC_DCMD(dmanr));
printf(" DDA = 0x%08x\n", REG_DMAC_DDA(dmanr));
printf(" DMADBR = 0x%08x\n", REG_DMAC_DMADBR);
}
