static void xhci_init(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script xhci_hc_init[] = { /* Initialize clock gating */ REG_SCRIPT_NEXT(xhci_clock_gating_script), /* Finalize XHCC1 and XHCC2 */ REG_PCI_RMW32(0x44, ~0x00000000, 0x83c00000), REG_PCI_RMW32(0x40, ~0x00800000, 0x80000000), /* Set USB2 Port Routing Mask */ REG_PCI_WRITE32(XHCI_USB2PRM, BYTM_USB2_PORT_MAP), /* Set USB3 Port Routing Mask */ REG_PCI_WRITE32(XHCI_USB3PRM, BYTM_USB3_PORT_MAP), /* * Disable ports if requested */ /* Open per-port disable control override */ REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~0, UPRWC_WR_EN), REG_PCI_WRITE32(XHCI_USB2PDO, config->usb2_port_disable_mask), REG_PCI_WRITE32(XHCI_USB3PDO, config->usb3_port_disable_mask), /* Close per-port disable control override */ REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN, 0), REG_SCRIPT_END }; /* Initialize XHCI controller for boot or resume path */ if (acpi_is_wakeup_s3()) reg_script_run_on_dev(dev, xhci_init_resume_script); else reg_script_run_on_dev(dev, xhci_init_boot_script); /* C0 steppings change iCLK/USB PLL VCO settings from 5 to 7 */ if (pattrs_get()->stepping == STEP_C0) { uint32_t reg = iosf_ushphy_read(USHPHY_CDN_PLL_CONTROL); reg |= 0x00700000; iosf_ushphy_write(USHPHY_CDN_PLL_CONTROL, reg); } /* Finalize Initialization */ reg_script_run_on_dev(dev, xhci_hc_init); /* Route all ports to XHCI if requested */ if (config->usb_route_to_xhci) xhci_route_all(dev); }
static void xhci_init(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script xhci_hc_init[] = { /* Initialize clock gating */ REG_SCRIPT_NEXT(xhci_clock_gating_script), /* Finalize XHCC1 and XHCC2 */ REG_PCI_RMW32(0x44, ~0x00000000, 0x83c00000), REG_PCI_RMW32(0x40, ~0x00800000, 0x80000000), /* Set USB2 Port Routing Mask */ REG_PCI_WRITE32(XHCI_USB2PRM, BYTM_USB2_PORT_MAP), /* Set USB3 Port Routing Mask */ REG_PCI_WRITE32(XHCI_USB3PRM, BYTM_USB3_PORT_MAP), /* * Disable ports if requested */ /* Open per-port disable control override */ REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~0, UPRWC_WR_EN), REG_PCI_WRITE32(XHCI_USB2PDO, config->usb2_port_disable_mask), REG_PCI_WRITE32(XHCI_USB3PDO, config->usb3_port_disable_mask), /* Close per-port disable control override */ REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN, 0), REG_SCRIPT_END }; /* Initialize XHCI controller for boot or resume path */ if (acpi_slp_type == 3) reg_script_run_on_dev(dev, xhci_init_resume_script); else reg_script_run_on_dev(dev, xhci_init_boot_script); /* Finalize Initialization */ reg_script_run_on_dev(dev, xhci_hc_init); /* Route all ports to XHCI if requested */ if (config->usb_route_to_xhci) xhci_route_all(dev); }
/* Ungating Display */ REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00000), REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffff0, 0xf00000, GFX_TIMEOUT), REG_SCRIPT_END }; static const struct reg_script gfx_post_vbios_script[] = { /* Deassert Render Force-Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80000000), REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0, GFX_TIMEOUT), /* Deassert Media Force-Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80000000), REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0, GFX_TIMEOUT), /* Set Lock bits */ REG_PCI_RMW32(GGC, 0xffffffff, 1), REG_PCI_RMW32(GSM_BASE, 0xffffffff, 1), REG_PCI_RMW32(GTT_BASE, 0xffffffff, 1), REG_SCRIPT_END }; static inline void gfx_run_script(device_t dev, const struct reg_script *ops) { reg_script_run_on_dev(dev, ops); } static void gfx_pre_vbios_init(device_t dev) { printk(BIOS_INFO, "GFX: Pre VBIOS Init\n"); gfx_run_script(dev, gpu_pre_vbios_script); }
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b1c, 0x03808033), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b34, 0x80000009), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3348, 0x022ddfff), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x334c, 0x00000001), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3358, 0x0001c000), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3380, 0x3f8ddbff), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3384, 0x0001c7e1), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x338c, 0x0001c7e1), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3398, 0x0001c000), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33a8, 0x00181900), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33dc, 0x00080000), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33e0, 0x00000001), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a20, 0x0000040c), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a24, 0x01010101), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a30, 0x01010101), REG_PCI_RMW32(0xac, ~0x00200000, 0), REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0410, 0x00000003), REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2618, 0x08000000), REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2300, 0x00000002), REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x2600, 0x00000008), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33b4, 0x00007001), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3350, 0x022ddfff), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3354, 0x00000001), /* Power Optimizer */ REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x08000000), REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x00000080), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b10, 0x0000883c), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b14, 0x1e0a4616), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b24, 0x40000005), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b20, 0x0005db01), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a80, 0x05145005),
REG_SCRIPT_END }; static const struct reg_script ehci_disable_script[] = { /* Clear Run/Stop Bit */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, USB2CMD, ~USB2CMD_RS, 0), /* Wait for HC Halted */ REG_RES_POLL32(PCI_BASE_ADDRESS_0, USB2STS, USB2STS_HCHALT, USB2STS_HCHALT, 10000), /* Disable Interrupts */ REG_PCI_OR32(EHCI_CMD_STS, INTRDIS), /* Disable Asynchronous and Periodic Scheduler */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, USB2CMD, ~(USB2CMD_ASE | USB2CMD_PSE), 0), /* Disable port wake */ REG_PCI_RMW32(EHCI_SBRN_FLA_PWC, ~(PORTWKIMP | PORTWKCAPMASK), 0), /* Set Function Disable bit in RCBA */ REG_MMIO_OR32(RCBA_BASE_ADDRESS + RCBA_FUNC_DIS, RCBA_EHCI_DIS), REG_SCRIPT_END }; static const struct reg_script ehci_hc_reset[] = { REG_RES_OR16(PCI_BASE_ADDRESS_0, USB2CMD, USB2CMD_HCRESET), REG_SCRIPT_END }; static void usb2_phy_init(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script usb2_phy_script[] = { /* USB3PHYInit() */
#include <soc/pci_devs.h> #include <soc/ramstage.h> static const struct reg_script init_ops[] = { /* Enable no snoop traffic. */ REG_PCI_OR16(0x78, 1 << 11), /* Configure HDMI codec connection. */ REG_PCI_OR32(0xc4, 1 << 1), REG_PCI_OR8(0x43, (1 << 3) | (1 << 6)), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0), REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0x00), /* Configure internal settings. */ REG_PCI_OR32(0xc0, 0x7 << 21), REG_PCI_OR32(0xc4, (0x3 << 26) | (1 << 13) | (1 << 10)), REG_PCI_WRITE32(0xc8, 0x82a30000), REG_PCI_RMW32(0xd0, ~(1 << 31), 0x0), /* Disable docking. */ REG_PCI_RMW8(0x4d, ~(1 << 7), 0), REG_SCRIPT_END, }; static const uint32_t hdmi_codec_verb_table[] = { /* coreboot specific header */ 0x80862882, /* vid did for hdmi codec */ 0x00000000, /* subsystem id */ 0x00000003, /* number of jacks */ /* pin widget 5 - port B */ 0x20471c10, 0x20471d00, 0x20471e56,
/* Initialize host controller */ REG_SCRIPT_NEXT(xhci_init_script), /* BAR + 0x80e0[16,9,6]=001b, leave bit 24=0 to prevent HC reset */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x01010200, 0x00000040), REG_SCRIPT_END }; const struct reg_script xhci_clock_gating_script[] = { /* ConfigureXhciClockGating() */ /* D20:F0:40[21:19,18,10:8]=000,1,001 (don't write byte 3) */ REG_PCI_RMW16(0x40, ~0x0600, 0x0100), REG_PCI_RMW8(0x42, ~0x38, 0x04), /* D20:F0:44[5:3]=001b */ REG_PCI_RMW16(0x44, ~0x0030, 0x0008), /* D20:F0:A0[19:18]=01b */ REG_PCI_RMW32(0xa0, ~0x00080000, 0x00040000), /* D20:F0:A4[15:0]=0x00 */ REG_PCI_WRITE16(0xa4, 0x0000), /* D20:F0:B0[21:17,14:13]=0000000b */ REG_PCI_RMW32(0xb0, ~0x00376000, 0x00000000), /* D20:F0:50[31:0]=0x0bce6e5f */ REG_PCI_WRITE32(0x50, 0x0bce6e5f), REG_SCRIPT_END }; /* Warm Reset a USB3 port */ static void xhci_reset_port_usb3(device_t dev, int port) { struct reg_script reset_port_usb3_script[] = { /* Issue Warm Port Rest to the port */ REG_RES_OR32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port),
OCFGPIMIXLOAD_1_0_MASK), REG_PCIE_AFE_AND(QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1, OCFGPIMIXLOAD_1_0_MASK), REG_SCRIPT_END }; static const struct reg_script pcie_bus_init_script[] = { /* Setup Message Bus Idle Counter (SBIC) values */ REG_PCI_RMW8(R_QNC_PCIE_IOSFSBCTL, ~B_QNC_PCIE_IOSFSBCTL_SBIC_MASK, V_PCIE_ROOT_PORT_SBIC_VALUE), REG_PCI_READ8(R_QNC_PCIE_IOSFSBCTL), /* Set the IPF bit in MCR2 */ REG_PCI_OR32(R_QNC_PCIE_MPC2, B_QNC_PCIE_MPC2_IPF), REG_PCI_READ32(R_QNC_PCIE_MPC2), /* Set up the Posted and Non Posted Request sizes for PCIe */ REG_PCI_RMW32(R_QNC_PCIE_CCFG, ~B_QNC_PCIE_CCFG_UPSD, (B_QNC_PCIE_CCFG_UNRS | B_QNC_PCIE_CCFG_UPRS)), REG_PCI_READ32(R_QNC_PCIE_CCFG), REG_SCRIPT_END }; void pcie_init(void) { /* Initialize the PCIe bridges */ reg_script_run(pcie_init_script); reg_script_run_on_dev(PCIE_PORT0_BDF, pcie_bus_init_script); reg_script_run_on_dev(PCIE_PORT1_BDF, pcie_bus_init_script); }