/* Warm Reset a USB3 port */ static void xhci_reset_port_usb3(device_t dev, int port) { struct reg_script reset_port_usb3_script[] = { /* Issue Warm Port Rest to the port */ REG_RES_OR32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), XHCI_USB3_PORTSC_WPR), /* Wait up to 100ms for it to complete */ REG_RES_POLL32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), XHCI_USB3_PORTSC_WRC, XHCI_USB3_PORTSC_WRC, XHCI_RESET_TIMEOUT), /* Clear change status bits, do not set PED */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), ~XHCI_USB3_PORTSC_PED, XHCI_USB3_PORTSC_CHST), REG_SCRIPT_END }; reg_script_run_on_dev(dev, reset_port_usb3_script); }
if (gms > ARRAY_SIZE(gms_size_map)) return; gmsize = gms_size_map[gms]; /* PcBase = BDSM + GMS Size - WOPCMSZ - PowerContextSize */ pcbase = pci_read_config32(dev, GSM_BASE) & 0xfff00000; pcbase += (gmsize-1) * wopcmsz - pcsize; pcbase |= 1; /* Lock */ write32((u32 *)(uintptr_t)(res->base + 0x182120), pcbase); } static const struct reg_script gfx_init_script[] = { /* Allow-Wake render/media wells */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x130090, ~1, 1), REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130094, 1, 1, GFX_TIMEOUT), /* Render Force-Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80008000), REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0x8000, GFX_TIMEOUT), /* Media Force-Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80008000), REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0x8000, GFX_TIMEOUT), /* Workaround - X0:261954/A0:261955 */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x182060, ~0xf, 1), /* * PowerMeter Weights */
#include <soc/ramstage.h> #include <soc/systemagent.h> #include <soc/intel/broadwell/chip.h> #include <vendorcode/google/chromeos/chromeos.h> #define GT_RETRY 1000 #define GT_CDCLK_337 0 #define GT_CDCLK_450 1 #define GT_CDCLK_540 2 #define GT_CDCLK_675 3 struct reg_script haswell_early_init_script[] = { /* Enable Force Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x00000020), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001), REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY), /* Enable Counters */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000016), /* GFXPAUSE settings */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00070020), /* ECO Settings */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0xa180, 0xff3fffff, 0x15000000), /* Enable DOP Clock Gating */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x000003fd), /* Enable Unit Level Clock Gating */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0x00000080),
REG_SCRIPT_END }; static const struct reg_script ehci_clock_gating_script[] = { /* Enable SB local clock gating */ REG_PCI_OR32(0x7c, 0x00004000), /* RCBA + 0x284=0xbe (step B0+) */ REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x284, 0x000000be), REG_SCRIPT_END }; static const struct reg_script ehci_disable_script[] = { /* Clear Run/Stop Bit */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, USB2CMD, ~USB2CMD_RS, 0), /* Wait for HC Halted */ REG_RES_POLL32(PCI_BASE_ADDRESS_0, USB2STS, USB2STS_HCHALT, USB2STS_HCHALT, 10000), /* Disable Interrupts */ REG_PCI_OR32(EHCI_CMD_STS, INTRDIS), /* Disable Asynchronous and Periodic Scheduler */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, USB2CMD, ~(USB2CMD_ASE | USB2CMD_PSE), 0), /* Disable port wake */ REG_PCI_RMW32(EHCI_SBRN_FLA_PWC, ~(PORTWKIMP | PORTWKCAPMASK), 0), /* Set Function Disable bit in RCBA */ REG_MMIO_OR32(RCBA_BASE_ADDRESS + RCBA_FUNC_DIS, RCBA_EHCI_DIS), REG_SCRIPT_END }; static const struct reg_script ehci_hc_reset[] = { REG_RES_OR16(PCI_BASE_ADDRESS_0, USB2CMD, USB2CMD_HCRESET), REG_SCRIPT_END