static void i2c_disable_resets(device_t dev) { /* Release the I2C devices from reset. */ static const struct reg_script ops[] = { REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x804, 0x3), REG_SCRIPT_END, }; #define CASE_I2C(name_) \ case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) switch (dev->path.pci.devfn) { CASE_I2C(I2C1) : CASE_I2C(I2C2) : CASE_I2C(I2C3) : CASE_I2C(I2C4) : CASE_I2C(I2C5) : CASE_I2C(I2C6) : CASE_I2C(I2C7) : printk(BIOS_DEBUG, "Releasing I2C device from reset.\n"); reg_script_run_on_dev(dev, ops); break; default: return; } }
static void gfx_panel_setup(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script gfx_pipea_init[] = { /* CONTROL */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_CONTROL), PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), /* POWER ON */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_ON_DELAYS), (config->gpu_pipea_port_select << 30 | config->gpu_pipea_power_on_delay << 16 | config->gpu_pipea_light_on_delay)), /* POWER OFF */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_OFF_DELAYS), (config->gpu_pipea_power_off_delay << 16 | config->gpu_pipea_light_off_delay)), /* DIVISOR */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_DIVISOR), ~0x1f, config->gpu_pipea_power_cycle_delay), REG_SCRIPT_END }; struct reg_script gfx_pipeb_init[] = { /* CONTROL */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_CONTROL), PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), /* POWER ON */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_ON_DELAYS), (config->gpu_pipeb_port_select << 30 | config->gpu_pipeb_power_on_delay << 16 | config->gpu_pipeb_light_on_delay)), /* POWER OFF */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_OFF_DELAYS), (config->gpu_pipeb_power_off_delay << 16 | config->gpu_pipeb_light_off_delay)), /* DIVISOR */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_DIVISOR), ~0x1f, config->gpu_pipeb_power_cycle_delay), REG_SCRIPT_END }; if (config->gpu_pipea_port_select) { printk(BIOS_INFO, "GFX: Initialize PIPEA\n"); reg_script_run_on_dev(dev, gfx_pipea_init); set_backlight_pwm(dev, PIPEA_REG(BACKLIGHT_CTL), config->gpu_pipea_pwm_freq_hz); } if (config->gpu_pipeb_port_select) { printk(BIOS_INFO, "GFX: Initialize PIPEB\n"); reg_script_run_on_dev(dev, gfx_pipeb_init); set_backlight_pwm(dev, PIPEB_REG(BACKLIGHT_CTL), config->gpu_pipeb_pwm_freq_hz); } }
gmsize = gms_size_map[gms]; /* PcBase = BDSM + GMS Size - WOPCMSZ - PowerContextSize */ pcbase = pci_read_config32(dev, GSM_BASE) & 0xfff00000; pcbase += (gmsize-1) * wopcmsz - pcsize; pcbase |= 1; /* Lock */ write32((u32 *)(uintptr_t)(res->base + 0x182120), pcbase); } static const struct reg_script gfx_init_script[] = { /* Allow-Wake render/media wells */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x130090, ~1, 1), REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130094, 1, 1, GFX_TIMEOUT), /* Render Force-Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80008000), REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0x8000, GFX_TIMEOUT), /* Media Force-Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80008000), REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0x8000, GFX_TIMEOUT), /* Workaround - X0:261954/A0:261955 */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x182060, ~0xf, 1), /* * PowerMeter Weights */ /* SET1 */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA800, 0x00000000),
#include <soc/cpu.h> #include <soc/pm.h> #include <soc/ramstage.h> #include <soc/systemagent.h> #include <soc/intel/broadwell/chip.h> #include <vendorcode/google/chromeos/chromeos.h> #define GT_RETRY 1000 #define GT_CDCLK_337 0 #define GT_CDCLK_450 1 #define GT_CDCLK_540 2 #define GT_CDCLK_675 3 struct reg_script haswell_early_init_script[] = { /* Enable Force Wake */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x00000020), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa188, 0x00010001), REG_RES_POLL32(PCI_BASE_ADDRESS_0, FORCEWAKE_ACK_HSW, 1, 1, GT_RETRY), /* Enable Counters */ REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa248, 0x00000016), /* GFXPAUSE settings */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00070020), /* ECO Settings */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0xa180, 0xff3fffff, 0x15000000), /* Enable DOP Clock Gating */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x000003fd),