static bool setup_scaling_configuration(
struct dce_transform *xfm_dce,
const struct scaler_data *data)
{
REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0);
if (data->taps.h_taps + data->taps.v_taps <= 2) {
/* Set bypass */
if (xfm_dce->xfm_mask->SCL_PSCL_EN != 0)
REG_UPDATE_2(SCL_MODE, SCL_MODE, 0, SCL_PSCL_EN, 0);
else
REG_UPDATE(SCL_MODE, SCL_MODE, 0);
return false;
}
REG_SET_2(SCL_TAP_CONTROL, 0,
SCL_H_NUM_OF_TAPS, data->taps.h_taps - 1,
SCL_V_NUM_OF_TAPS, data->taps.v_taps - 1);
if (data->format <= PIXEL_FORMAT_GRPH_END)
REG_UPDATE(SCL_MODE, SCL_MODE, 1);
else
REG_UPDATE(SCL_MODE, SCL_MODE, 2);
if (xfm_dce->xfm_mask->SCL_PSCL_EN != 0)
REG_UPDATE(SCL_MODE, SCL_PSCL_EN, 1);
/* 1 - Replace out of bound pixels with edge */
REG_SET(SCL_CONTROL, 0, SCL_BOUNDARY_MODE, 1);
return true;
}
static void dce110_se_setup_dp_audio(
struct stream_encoder *enc)
{
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
/* --- DP Audio packet configurations --- */
/* ATP Configuration */
REG_SET(DP_SEC_AUD_N, 0,
DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
/* Async/auto-calc timestamp mode */
REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
/* --- The following are the registers
* copied from the SetupHDMI --- */
/* AFMT_AUDIO_PACKET_CONTROL */
REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
/* AFMT_AUDIO_PACKET_CONTROL2 */
/* Program the ATP and AIP next */
REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
AFMT_AUDIO_LAYOUT_OVRD, 0,
AFMT_60958_OSF_OVRD, 0);
/* AFMT_INFOFRAME_CONTROL0 */
REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
/* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
}
uint32_t exec_reg_set(t_rmatch *m, t_reg_set const *reg, uint32_t offset)
{
uint32_t const min = reg->reg.min + offset;
uint32_t const max = MIN(reg->reg.max + offset, m->str.length);
uint32_t const start = offset;
uint32_t tmp;
if (min > m->str.length)
return (REG_FAIL);
while (true)
{
if (offset >= min && reg->reg.flags & REG_F_MINIMAL
&& (tmp = exec_reg_next(m, V(reg), start, offset)) != REG_FAIL)
return (tmp);
if (offset >= max)
break ;
if (!(BOOL_OF(REG_SET()
|| (reg->reg.flags & REG_F_ICASE && REG_SET(LOWER)))
^ BOOL_OF(reg->reg.flags & REG_F_NOT)))
break ;
offset++;
}
if (!(reg->reg.flags & REG_F_MINIMAL))
while (offset >= min && offset <= max)
if ((tmp = exec_reg_next(m, V(reg), start, offset--)) != REG_FAIL)
return (tmp);
return (REG_FAIL);
}
static void hubp1_set_vm_system_aperture_settings(struct hubp *hubp,
struct vm_system_aperture_param *apt)
{
struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 12;
mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 12;
REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0,
MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, aperture_default_system, /* 1 = system physical memory */
MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part);
REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0,
MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part);
REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0,
MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mc_vm_apt_low.high_part);
REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0,
MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mc_vm_apt_low.low_part);
REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0,
MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mc_vm_apt_high.high_part);
REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0,
MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mc_vm_apt_high.low_part);
}
static void program_gamut_remap(
struct dce_transform *xfm_dce,
const uint16_t *reg_val)
{
if (reg_val) {
REG_SET_2(GAMUT_REMAP_C11_C12, 0,
GAMUT_REMAP_C11, reg_val[0],
GAMUT_REMAP_C12, reg_val[1]);
REG_SET_2(GAMUT_REMAP_C13_C14, 0,
GAMUT_REMAP_C13, reg_val[2],
GAMUT_REMAP_C14, reg_val[3]);
REG_SET_2(GAMUT_REMAP_C21_C22, 0,
GAMUT_REMAP_C21, reg_val[4],
GAMUT_REMAP_C22, reg_val[5]);
REG_SET_2(GAMUT_REMAP_C23_C24, 0,
GAMUT_REMAP_C23, reg_val[6],
GAMUT_REMAP_C24, reg_val[7]);
REG_SET_2(GAMUT_REMAP_C31_C32, 0,
GAMUT_REMAP_C31, reg_val[8],
GAMUT_REMAP_C32, reg_val[9]);
REG_SET_2(GAMUT_REMAP_C33_C34, 0,
GAMUT_REMAP_C33, reg_val[10],
GAMUT_REMAP_C34, reg_val[11]);
REG_SET(GAMUT_REMAP_CONTROL, 0, GRPH_GAMUT_REMAP_MODE, 1);
} else
REG_SET(GAMUT_REMAP_CONTROL, 0, GRPH_GAMUT_REMAP_MODE, 0);
}
static int
jz4780_clk_pll_set_freq(struct clknode *clk, uint64_t fin,
uint64_t *fout, int flags, int *stop)
{
struct jz4780_clk_pll_sc *sc;
uint32_t reg, m, n, od;
int rv;
sc = clknode_get_softc(clk);
/* Should be able to figure all clocks with m & n only */
od = 1;
m = MIN((uint32_t)(*fout / MHZ), (1u << CGU_PLL_M_WIDTH));
m = MIN(m, 1);
n = MIN((uint32_t)(fin / MHZ), (1u << CGU_PLL_N_WIDTH));
n = MIN(n, 1);
if (flags & CLK_SET_DRYRUN) {
if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) &&
(*fout != (((fin / n) * m) / od)))
return (ERANGE);
*fout = ((fin / n) * m) / od;
return (0);
}
CLK_LOCK(sc);
reg = CLK_RD_4(sc, sc->clk_reg);
/* Set the calculated values */
reg = REG_SET(reg, CGU_PLL_M, m - 1);
reg = REG_SET(reg, CGU_PLL_N, n - 1);
reg = REG_SET(reg, CGU_PLL_OD, od - 1);
/* Enable the PLL */
reg = REG_SET(reg, CGU_PLL_EN, 1);
reg = REG_SET(reg, CGU_PLL_BP, 0);
/* Initiate the change */
CLK_WR_4(sc, sc->clk_reg, reg);
/* Wait for PLL to lock */
rv = jz4780_clk_pll_wait_lock(sc);
CLK_UNLOCK(sc);
if (rv != 0)
return (rv);
*fout = ((fin / n) * m) / od;
return (0);
}
////////////////////////////////////////////////////////////////////////////////
// UserEarlyConfig()函数在启动代码中执行，这时还没有RTOS存在。
////////////////////////////////////////////////////////////////////////////////
bool_t UserEarlyConfig(void)
{
// 尽早初始化中断控制模块使之可用。
if(!ICOLL_Init()){
return FALSE;
}
// 将所有USART的时钟源设置为PLL (BUG：UART只能用12MHZ晶振作时钟源)。
outl(1, REG_SET(HW_UARTCLKSEL));
outl(1, REG_CLR(HW_UARTCLKUEN));
outl(1, REG_SET(HW_UARTCLKUEN));
return TRUE;
}
void SysClkConfig(void)
{
u32_t utmp = 0;
// 初始化系统时钟
outl(1<<2, REG_SET(HW_AHBCLKCTRL0)); // SRAM模块时钟使能
outl(3<<9, REG_SET(HW_AHBCLKCTRL0)); // DMA0,1模块时钟使能
outl(1<<8, REG_SET(HW_AHBCLKCTRL1)); // 中断控制模块时钟使能
outl(inl(HW_PDRUNCFG)&0xFFFFFFFA, HW_PDRUNCFG); // 片外12M晶振和系统PLL上电
outl(2, HW_CPUCLKDIV); // CPUCLK = PLLCLK/2
outl(2, HW_SYSAHBCLKDIV); // AHBCLK = CPUCLK/2
outl(480, HW_SYSPLLCTRL); // PLLCLK = 480MHz
while((inl(HW_SYSPLLSTAT)&0x1) == 0x0){ // 等待系统PLL锁定
if(utmp++ > 0x100000){
break;
}
}
util_fastloop(40*100); // 等待系统时钟稳定100us
outl(1, HW_MAINCLKSEL); // 选择系统PLL为CPU时钟
outl(0, HW_MAINCLKUEN); // 先写0，再写1才能让更新生效
outl(1, HW_MAINCLKUEN);
// 初始化片内SDRAM
outl(1<<6, REG_SET(HW_AHBCLKCTRL0)); // 使能EMI模块时钟
utmp = ((1<<3) // Bank地址位宽=2
|(12<<5) // 行地址位宽=13
|(8<<9) // 行地址位宽=9
|(0<<13)); // 数据线位宽=16
outl(utmp, HW_EMI_SCONR);
utmp = (inl(HW_EMI_CTRL) & 0xFFF1E0FF);
utmp |= ((5<<8) // EMI内部hclk_d延时调整
|(1<<17) // 片内SDRAM使能
|(2<<18)); // 片内SDRAM对应EMI片选2
outl(utmp, HW_EMI_CTRL);
outl(0x20000000, HW_EMI_SCSLR2_LOW); // EMI片选2的物理地址是0x20000000
outl(0xa, HW_EMI_SMSKR2); // EMI片选2的内存大小为32MB
utmp = ((0<<27) // extended_t_xsr
|(0<<26) // extended_cas_latency
|(9<<22) // t_rc=10 clks
|(2<<18) // t_xsr=3 clks
|(6<<14) // t_rcar=7 clks
|(1<<12) // t_wr=2 clks
|(3<<9) // t_rp=4 clks
|(3<<6) // t_rcd=4 clks
|(6<<2) // t_ras_min=7 clks
|(1<<0)); // cas_latency=2 clks
// 0x024996d9 = 00000,0,1001,0010,0110,01,011,011,0110,01
outl(utmp, HW_EMI_STMG0R);
outl(0x00542b4f, HW_EMI_SMTMGR_SET0);
outl(inl(HW_EMI_SCTLR)|(1<<9), HW_EMI_SCTLR);
}
static void dpp1_cm_set_regamma_mode(
struct dpp *dpp_base,
enum opp_regamma mode)
{
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
uint32_t re_mode = 0;
uint32_t obuf_bypass = 0; /* need for pipe split */
uint32_t obuf_hupscale = 0;
switch (mode) {
case OPP_REGAMMA_BYPASS:
re_mode = 0;
break;
case OPP_REGAMMA_SRGB:
re_mode = 1;
break;
case OPP_REGAMMA_3_6:
re_mode = 2;
break;
case OPP_REGAMMA_USER:
re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4;
dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe;
break;
default:
break;
}
REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode);
REG_UPDATE_2(OBUF_CONTROL,
OBUF_BYPASS, obuf_bypass,
OBUF_H_2X_UPSCALE_EN, obuf_hupscale);
}
//lectura por referencia en un relativo por numero de celda
//
//IMPORTANTE: tengase en cuenta que si se quisieran obtener todos los registros
//del archivo directo, hay que pedir al directo todas las posibles claves con un ciclo,
//verificando tambien los errores sobre claves que no puedan existir
int direct_read(const char * filename, int student_id) {
char[20] name;
void * reg = malloc(REG_SIZEOF(schema_students));
int status;
int fd = D_OPEN(filename, READ);
if (fd == RES_ERROR) {
free(reg);
return -1;
}
//movemos al registro de intercambio el id del estudiante que queremos encontrar
REG_SET(reg, schema_students,"PADRON",student_id);
status = D_READ(fd, reg);
if (status == RES_NO_EXISTE || status == RES_ERROR) {
free(reg);
D_CLOSE(fd);
return -2;
}
//obtenemos los datos del registro de intercambio
REG_GET(reg, schema_students, "PADRON,NOMBRE", &student_id, &name);
printf("%d %s", student_id, name);
//liberamos recursos
free(reg);
D_CLOSE(fd);
return 0;
}
static void set_denormalization(
struct dce_transform *xfm_dce,
enum dc_color_depth depth)
{
int denorm_mode = 0;
switch (depth) {
case COLOR_DEPTH_666:
/* 63/64 for 6 bit output color depth */
denorm_mode = 1;
break;
case COLOR_DEPTH_888:
/* Unity for 8 bit output color depth
* because prescale is disabled by default */
denorm_mode = 0;
break;
case COLOR_DEPTH_101010:
/* 1023/1024 for 10 bit output color depth */
denorm_mode = 3;
break;
case COLOR_DEPTH_121212:
/* 4095/4096 for 12 bit output color depth */
denorm_mode = 5;
break;
case COLOR_DEPTH_141414:
case COLOR_DEPTH_161616:
default:
/* not valid used case! */
break;
}
REG_SET(DENORM_CONTROL, 0, DENORM_MODE, denorm_mode);
}
void lcd_disable(void)
{
debug("lcd_disable\n");
/* Disable clocks to EPDC */
REG_SET(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_CLKGATE);
}
void CAN_Ctrl::init(uint32_t baudrate){
if(!initialized){
initialized=true;
can_init(can, CAN_LAST_MB);
imx_flexcan canmodule;
can_set_can_attributes(&canmodule,mapToFlexcanBitrate(baudrate),can);
can_update_bitrate(&canmodule);
for(int i=0;i<CAN_NUMBER_OF_BUFFERS;i++){
can_mb_int_ack(can,i);
}
//configure fifo
HW_FLEXCAN_MCR_SET(can->instance,BM_FLEXCAN_MCR_FEN); //set RFEN
HW_FLEXCAN_MCR_SET(can->instance,BM_FLEXCAN_MCR_BCC);//set IRMQ
HW_FLEXCAN_MCR_CLR(can->instance,BM_FLEXCAN_MCR_IDAM); // filter format A
REG_SET(REG_RXFGMASK(can->base),~0);
//conif RFFN
REG_SET(REG_CTRL2(can->base),0xF <<REG_CTRL2_RFFN_SHIFT);
//configure other flags
HW_FLEXCAN_MCR_SET(can->instance,BM_FLEXCAN_MCR_SRX_DIS); //No self recv
REG_SET(REG_CTRL2(can->base),REG_CTRL2_RRS_MASK);
//configure irq
irq_hdlr_t handler;
uint32_t irqid;
if(this==&CANs[0]){
irqid=IMX_INT_FLEXCAN1;
handler=&CAN1_IRQHandler;
}else if(this==&CANs[1]){
irqid=IMX_INT_FLEXCAN2;
handler=&CAN2_IRQHandler;
}
register_interrupt_routine(irqid,handler);
enable_interrupt(irqid,cpu_get_current(),128);
gic_set_irq_security(irqid,false);
setupFilters();
can_exit_freeze(can);
can_enable_mb_interrupt(can,FIFO_FLAG_DATARDY);
}
}
void dce110_opp_set_regamma_mode(struct transform *xfm,
enum opp_regamma mode)
{
struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
REG_SET(REGAMMA_CONTROL, 0,
GRPH_REGAMMA_MODE, mode);
}
static void write_indirect_azalia_reg(struct audio *audio,
uint32_t reg_index,
uint32_t reg_data)
{
struct dce_audio *aud = DCE_AUD(audio);
/* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */
REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,
AZALIA_ENDPOINT_REG_INDEX, reg_index);
/* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */
REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0,
AZALIA_ENDPOINT_REG_DATA, reg_data);
DC_LOG_HW_AUDIO("AUDIO:write_indirect_azalia_reg: index: %u data: %u\n",
reg_index, reg_data);
}
static void set_clocks(void)
{
u32 ssp_source_clk, ssp_clk;
u32 ssp_div = 1;
u32 val = 0;
/*
* Configure 480Mhz IO clock
*/
/* Ungate IO_CLK and set divider */
REG_CLR(CLKCTRL_BASE + CLKCTRL_FRAC, FRAC_CLKGATEIO);
REG_CLR(CLKCTRL_BASE + CLKCTRL_FRAC, 0x3f << FRAC_IOFRAC);
REG_SET(CLKCTRL_BASE + CLKCTRL_FRAC, IO_DIVIDER << FRAC_IOFRAC);
/*
* Set SSP CLK to desired value
*/
/* Calculate SSP_CLK divider relatively to 480Mhz IO_CLK*/
ssp_source_clk = 480 * MHz;
ssp_clk = CONFIG_SSP_CLK;
ssp_div = (ssp_source_clk + ssp_clk - 1) / ssp_clk;
/* Enable SSP clock */
val = REG_RD(CLKCTRL_BASE + CLKCTRL_SSP);
val &= ~SSP_CLKGATE;
REG_WR(CLKCTRL_BASE + CLKCTRL_SSP, val);
/* Wait while clock is gated */
while (REG_RD(CLKCTRL_BASE + CLKCTRL_SSP) & SSP_CLKGATE)
;
/* Set SSP clock divider */
val &= ~(0x1ff << SSP_DIV);
val |= ssp_div << SSP_DIV;
REG_WR(CLKCTRL_BASE + CLKCTRL_SSP, val);
/* Wait until new divider value is set */
while (REG_RD(CLKCTRL_BASE + CLKCTRL_SSP) & SSP_BUSY)
;
/* Set SSP clock source to IO_CLK */
REG_SET(CLKCTRL_BASE + CLKCTRL_CLKSEQ, CLKSEQ_BYPASS_SSP);
REG_CLR(CLKCTRL_BASE + CLKCTRL_CLKSEQ, CLKSEQ_BYPASS_SSP);
}
int epdc_ctrl_init(void *lcdbase)
{
/*
* We rely on lcdbase being a physical address, i.e., either MMU off,
* or 1-to-1 mapping. Might want to add some virt2phys here.
*/
if (!lcdbase)
return -1;
eink_color_fg = 0xFF;
eink_color_bg = 0xFF;
/* Reset */
REG_SET(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_SFTRST);
while (!(REG_RD(EPDC_BASE, EPDC_CTRL) & EPDC_CTRL_CLKGATE))
;
REG_CLR(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_SFTRST);
/* Enable clock gating (clear to enable) */
REG_CLR(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_CLKGATE);
while (REG_RD(EPDC_BASE, EPDC_CTRL) &
(EPDC_CTRL_SFTRST | EPDC_CTRL_CLKGATE))
;
debug("resolution %dx%d, bpp %d\n", (int)panel_info.vl_col,
(int)panel_info.vl_row, NBITS(panel_info.vl_bpix));
/* Set framebuffer pointer */
REG_WR(EPDC_BASE, EPDC_UPD_ADDR, (u32)lcdbase);
#if 0
/* Set Working Buffer pointer */
REG_WR(EPDC_BASE, EPDC_WB_ADDR, panel_info.epdc_data.working_buf_addr);
/* Set Waveform Buffer pointer */
REG_WR(EPDC_BASE, EPDC_WVADDR, panel_info.epdc_data.waveform_buf_addr);
#endif
/* Set waveform and working buffer, they will be changed later */
REG_WR(EPDC_BASE, EPDC_WVADDR, (unsigned long)CONFIG_TEMP_INIT_WAVEFORM_ADDR);
REG_WR(EPDC_BASE, EPDC_WB_ADDR, (unsigned long)CONFIG_WORKING_BUF_ADDR);
#if 0
/* Get waveform data address and offset */
int data_offs = setup_waveform_file();
if(data_offs == -1) {
printf("Can't load waveform data!\n");
return -1;
}
#endif
/* Initialize EPDC, passing pointer to EPDC registers */
epdc_init_settings();
epdc_initialized = 1;
return;
}
static void hubp1_set_vm_context0_settings(struct hubp *hubp,
const struct vm_context0_param *vm0)
{
struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
/* pte base */
REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, 0,
VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, vm0->pte_base.high_part);
REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, 0,
VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, vm0->pte_base.low_part);
/* pte start */
REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, 0,
VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, vm0->pte_start.high_part);
REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, 0,
VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, vm0->pte_start.low_part);
/* pte end */
REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, 0,
VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, vm0->pte_end.high_part);
REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, 0,
VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, vm0->pte_end.low_part);
/* fault handling */
REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0,
VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, vm0->fault_default.high_part,
VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, context0_default_system);
REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0,
VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, vm0->fault_default.low_part);
/* control: enable VM PTE*/
REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
ENABLE_L1_TLB, 1,
SYSTEM_ACCESS_MODE, 3);
}
static void program_multi_taps_filter(
struct dce_transform *xfm_dce,
int taps,
const uint16_t *coeffs,
enum ram_filter_type filter_type)
{
int phase, pair;
int array_idx = 0;
int taps_pairs = (taps + 1) / 2;
int phases_to_program = SCL_PHASES / 2 + 1;
uint32_t power_ctl = 0;
if (!coeffs)
return;
/*We need to disable power gating on coeff memory to do programming*/
if (REG(DCFE_MEM_PWR_CTRL)) {
power_ctl = REG_READ(DCFE_MEM_PWR_CTRL);
REG_SET(DCFE_MEM_PWR_CTRL, power_ctl, SCL_COEFF_MEM_PWR_DIS, 1);
REG_WAIT(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, 0, 1, 10);
}
for (phase = 0; phase < phases_to_program; phase++) {
/*we always program N/2 + 1 phases, total phases N, but N/2-1 are just mirror
phase 0 is unique and phase N/2 is unique if N is even*/
for (pair = 0; pair < taps_pairs; pair++) {
uint16_t odd_coeff = 0;
uint16_t even_coeff = coeffs[array_idx];
REG_SET_3(SCL_COEF_RAM_SELECT, 0,
SCL_C_RAM_FILTER_TYPE, filter_type,
SCL_C_RAM_PHASE, phase,
SCL_C_RAM_TAP_PAIR_IDX, pair);
if (taps % 2 && pair == taps_pairs - 1)
array_idx++;
else {
odd_coeff = coeffs[array_idx + 1];
array_idx += 2;
}
REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0,
SCL_C_RAM_EVEN_TAP_COEF_EN, 1,
SCL_C_RAM_EVEN_TAP_COEF, even_coeff,
SCL_C_RAM_ODD_TAP_COEF_EN, 1,
SCL_C_RAM_ODD_TAP_COEF, odd_coeff);
}
}
/*We need to restore power gating on coeff memory to initial state*/
if (REG(DCFE_MEM_PWR_CTRL))
REG_WRITE(DCFE_MEM_PWR_CTRL, power_ctl);
}
static void program_scl_ratios_inits(
struct dce_transform *xfm_dce,
struct scl_ratios_inits *inits)
{
REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,
SCL_H_SCALE_RATIO, inits->h_int_scale_ratio);
REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,
SCL_V_SCALE_RATIO, inits->v_int_scale_ratio);
REG_SET_2(SCL_HORZ_FILTER_INIT, 0,
SCL_H_INIT_INT, inits->h_init.integer,
SCL_H_INIT_FRAC, inits->h_init.fraction);
REG_SET_2(SCL_VERT_FILTER_INIT, 0,
SCL_V_INIT_INT, inits->v_init.integer,
SCL_V_INIT_FRAC, inits->v_init.fraction);
REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0);
}
void dpp_reset(struct dpp *dpp_base)
{
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
dpp->filter_h_c = NULL;
dpp->filter_v_c = NULL;
dpp->filter_h = NULL;
dpp->filter_v = NULL;
/* set boundary mode to 0 */
REG_SET(DSCL_CONTROL, 0, SCL_BOUNDARY_MODE, 0);
}
/*******************************************************************************
* set_round
*
* @brief
* Programs Round/Truncate
*
* @param [in] mode :round or truncate
* @param [in] depth :bit depth to round/truncate to
OUT_ROUND_TRUNC_MODE 3:0 0xA Output data round or truncate mode
POSSIBLE VALUES:
00 - truncate to u0.12
01 - truncate to u0.11
02 - truncate to u0.10
03 - truncate to u0.9
04 - truncate to u0.8
05 - reserved
06 - truncate to u0.14
07 - truncate to u0.13 set_reg_field_value(
value,
clamp_max,
OUT_CLAMP_CONTROL_R_CR,
OUT_CLAMP_MAX_R_CR);
08 - round to u0.12
09 - round to u0.11
10 - round to u0.10
11 - round to u0.9
12 - round to u0.8
13 - reserved
14 - round to u0.14
15 - round to u0.13
******************************************************************************/
static void set_round(
struct dce_transform *xfm_dce,
enum dcp_out_trunc_round_mode mode,
enum dcp_out_trunc_round_depth depth)
{
int depth_bits = 0;
int mode_bit = 0;
/* set up bit depth */
switch (depth) {
case DCP_OUT_TRUNC_ROUND_DEPTH_14BIT:
depth_bits = 6;
break;
case DCP_OUT_TRUNC_ROUND_DEPTH_13BIT:
depth_bits = 7;
break;
case DCP_OUT_TRUNC_ROUND_DEPTH_12BIT:
depth_bits = 0;
break;
case DCP_OUT_TRUNC_ROUND_DEPTH_11BIT:
depth_bits = 1;
break;
case DCP_OUT_TRUNC_ROUND_DEPTH_10BIT:
depth_bits = 2;
break;
case DCP_OUT_TRUNC_ROUND_DEPTH_9BIT:
depth_bits = 3;
break;
case DCP_OUT_TRUNC_ROUND_DEPTH_8BIT:
depth_bits = 4;
break;
default:
depth_bits = 4;
BREAK_TO_DEBUGGER(); /* Invalid dcp_out_trunc_round_depth */
}
/* set up round or truncate */
switch (mode) {
case DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE:
mode_bit = 0;
break;
case DCP_OUT_TRUNC_ROUND_MODE_ROUND:
mode_bit = 1;
break;
default:
BREAK_TO_DEBUGGER(); /* Invalid dcp_out_trunc_round_mode */
}
depth_bits |= mode_bit << 3;
REG_SET(OUT_ROUND_CONTROL, 0, OUT_ROUND_TRUNC_MODE, depth_bits);
}
void systick_init(void) {
/* Set the reload counter to tick every 1ms */
REG_SET_MASK(SYSTICK_RELOAD, MAPLE_RELOAD_VAL);
// SYSTICK_RELOAD = MAPLE_RELOAD_VAL;
/* Clock the system timer with the core clock
* and turn it on, interrrupt every 1ms to keep track of millis()*/
REG_SET(SYSTICK_CSR, SYSTICK_SRC_HCLK |
SYSTICK_ENABLE |
SYSTICK_TICKINT);
// SYSTICK_CSR = SYSTICK_SRC_HCLK |
// SYSTICK_ENABLE |
// SYSTICK_TICKINT;
}
void enable_interrupt(uint8 channel) {
// copied from exti_attach_interrupt() in libmaple/exti.c
// TODO: refactor exti_attach_interrupt() to separate this into a separate function and eliminate duplication
/* Configure the enable interrupt bits for the NVIC */
switch (channel) {
case EXTI0:
case EXTI1:
case EXTI2:
case EXTI3:
case EXTI4:
REG_SET(NVIC_ISER0, BIT(channel + 6));
break;
/* EXTI5-9 map to the same isr */
case EXTI5:
case EXTI6:
case EXTI7:
case EXTI8:
case EXTI9:
REG_SET(NVIC_ISER0, BIT(23));
break;
/* EXTI10-15 map to the same isr */
case EXTI10:
case EXTI11:
case EXTI12:
case EXTI13:
case EXTI14:
case EXTI15:
REG_SET(NVIC_ISER1, BIT(8));
break;
}
}
void lcd_ctrl_init(void *lcdbase)
{
/*
* We rely on lcdbase being a physical address, i.e., either MMU off,
* or 1-to-1 mapping. Might want to add some virt2phys here.
*/
if (!lcdbase)
return;
lcd_color_fg = 0xFF;
lcd_color_bg = 0xFF;
/* Reset */
REG_SET(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_SFTRST);
while (!(REG_RD(EPDC_BASE, EPDC_CTRL) & EPDC_CTRL_CLKGATE))
;
REG_CLR(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_SFTRST);
/* Enable clock gating (clear to enable) */
REG_CLR(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_CLKGATE);
while (REG_RD(EPDC_BASE, EPDC_CTRL) &
(EPDC_CTRL_SFTRST | EPDC_CTRL_CLKGATE))
;
debug("resolution %dx%d, bpp %d\n", (int)panel_info.vl_col,
(int)panel_info.vl_row, NBITS(panel_info.vl_bpix));
/* Set framebuffer pointer */
REG_WR(EPDC_BASE, EPDC_UPD_ADDR, (u32)lcdbase);
/* Set Working Buffer pointer */
REG_WR(EPDC_BASE, EPDC_WB_ADDR, panel_info.epdc_data.working_buf_addr);
/* Get waveform data address and offset */
if (setup_waveform_file()) {
printf("Can't load waveform data!\n");
return;
}
/* Set Waveform Buffer pointer */
REG_WR(EPDC_BASE, EPDC_WVADDR,
panel_info.epdc_data.waveform_buf_addr);
/* Initialize EPDC, passing pointer to EPDC registers */
epdc_init_settings();
return;
}
void epd_disable(void)
{
debug("epd_disable\n");
u32 val;
#if 1
/*clear the INT*/
val = REG_RD(EPDC_BASE, EPDC_IRQ_MASK);
val |= (1<<0);
REG_WR(EPDC_BASE, EPDC_IRQ_MASK, val);
val = REG_RD(EPDC_BASE, EPDC_IRQ_CLR);
val |= (1<<0);
REG_WR(EPDC_BASE, EPDC_IRQ_CLR,val);
#endif
/* Disable clocks to EPDC */
REG_SET(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_CLKGATE);
debug("EPDC LUT STATUS %08x\n",REG_RD(EPDC_BASE,EPDC_STATUS_LUTS));
}
static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index)
{
struct dce_audio *aud = DCE_AUD(audio);
uint32_t value = 0;
/* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */
REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0,
AZALIA_ENDPOINT_REG_INDEX, reg_index);
/* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */
value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA);
DC_LOG_HW_AUDIO("AUDIO:read_indirect_azalia_reg: index: %u data: %u\n",
reg_index, value);
return value;
}
int timer_init(void)
{
u32 val;
/*
* Reset Timers and Rotary Encoder module
*/
/* Clear SFTRST */
REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 31);
while (REG_RD(TIMROT_BASE + ROTCTRL) & (1 << 31))
;
/* Clear CLKGATE */
REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 30);
/* Set SFTRST and wait until CLKGATE is set */
REG_SET(TIMROT_BASE + ROTCTRL, 1 << 31);
while (!(REG_RD(TIMROT_BASE + ROTCTRL) & (1 << 30)))
;
/* Clear SFTRST and CLKGATE */
REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 31);
REG_CLR(TIMROT_BASE + ROTCTRL, 1 << 30);
/*
* Now initialize timer
*/
/* Set fixed_count to 0 */
REG_WR(TIMROT_BASE + TIMCOUNT, 0);
/* set UPDATE bit and 1Khz frequency */
REG_WR(TIMROT_BASE + TIMCTRL,
TIMCTRL_RELOAD | TIMCTRL_UPDATE | TIMCTRL_SELECT_1KHZ);
/* Set fixed_count to maximal value */
REG_WR(TIMROT_BASE + TIMCOUNT, TIMER_LOAD_VAL);
/* init the timestamp and lastdec value */
reset_timer_masked();
return 0;
}
void asm_usart_gpio_init(void)
{
// enable IOCONFIG GPIO
outl(((1UL<<25) | (1UL<<4)) ,REG_SET(HW_AHBCLKCTRL0));
#ifdef RT_USING_UART0
HW_SetPinMux(14, 0, 5);
HW_SetPinMux(14, 1, 5);
#endif
#ifdef RT_USING_UART3
HW_SetPinMux(8, 6, 2);
HW_SetPinMux(8, 7, 2);
#endif
#ifdef RT_USING_UART4
HW_SetPinMux(3, 0, 2);
HW_SetPinMux(3, 1, 2);
#endif
}
static void dce110_se_audio_setup(
struct stream_encoder *enc,
unsigned int az_inst,
struct audio_info *audio_info)
{
struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
uint32_t speakers = 0;
uint32_t channels = 0;
ASSERT(audio_info);
if (audio_info == NULL)
/* This should not happen.it does so we don't get BSOD*/
return;
speakers = audio_info->flags.info.ALLSPEAKERS;
channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
/* setup the audio stream source select (audio -> dig mapping) */
REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);
/* Channel allocation */
REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
}
