void main() {
BOOL on=FALSE;
unsigned int size=0;
LED6 = 0;
REVCTL=0; // not using advanced endpoint controls
on=0;
lcount=0;
got_sud=FALSE;
icount=0;
gotbuf=FALSE;
bytes=0;
// renumerate
RENUMERATE_UNCOND();
SETCPUFREQ(CLK_48M);
sio0_init(57600);
USE_USB_INTS();
ENABLE_SUDAV();
ENABLE_SOF();
ENABLE_HISPEED();
ENABLE_USBRESET();
// only valid endpoints are 2/6
EP2CFG = 0xA2; // 10100010
SYNCDELAY();
EP6CFG = 0xE2; // 11100010
SYNCDELAY();
EP1INCFG &= ~bmVALID;
SYNCDELAY();
EP1OUTCFG &= ~bmVALID;
SYNCDELAY();
EP4CFG &= ~bmVALID;
SYNCDELAY();
EP8CFG &= ~bmVALID;
SYNCDELAY();
// arm ep2
EP2BCL = 0x80; // write once
SYNCDELAY();
EP2BCL = 0x80; // do it again
EA=1; // global interrupt enable
OEB |= 0x01; // set PB0 as output
LED6 = 0;
eeprom_write_local(LG_PROM, 0, IIC_SIZE, fx2_c0);
while(TRUE) {
if ( got_sud ) {
printf ( "Handle setupdata\n" );
handle_setupdata();
got_sud=FALSE;
}
if ( !(EP2468STAT & bmEP2EMPTY) ) { // EP2 received data
if ( !(EP2468STAT & bmEP6FULL) ) { // wait for at least one
// empty buffer
WORD i;
bytes = MAKEWORD(EP2BCH,EP2BCL);
for (i=0;i<bytes;++i) {
EP6FIFOBUF[i] = 0x00;
// arm ep6 out
EP6BCH=MSB(bytes);
SYNCDELAY();
EP6BCL=LSB(bytes);
REARM(); // re-arm ep2
}
}
}
//delay(40);
if (LED6) {LED6 = 0;} else {LED6 =1;}
}
}
void main() {
REVCTL=0; // not using advanced endpoint controls
d2off();
on=0;
lcount=0;
got_sud=FALSE;
icount=0;
gotbuf=FALSE;
bytes=0;
// renumerate
RENUMERATE_UNCOND();
SETCPUFREQ(CLK_48M);
SETIF48MHZ();
sio0_init(57600);
USE_USB_INTS();
ENABLE_SUDAV();
ENABLE_SOF();
ENABLE_HISPEED();
ENABLE_USBRESET();
// only valid endpoints are 2/6
EP2CFG = 0xA2; // 10100010
SYNCDELAY;
EP6CFG = 0xE2; // 11100010
SYNCDELAY;
EP1INCFG &= ~bmVALID;
SYNCDELAY;
EP1OUTCFG &= ~bmVALID;
SYNCDELAY;
EP4CFG &= ~bmVALID;
SYNCDELAY;
EP8CFG &= ~bmVALID;
SYNCDELAY;
// arm ep2
EP2BCL = 0x80; // write once
SYNCDELAY;
EP2BCL = 0x80; // do it again
// make it so we enumberate
EA=1; // global interrupt enable
printf ( "Done initializing stuff\n" );
d3off();
while(TRUE) {
if ( got_sud ) {
printf ( "Handle setupdata\n" );
handle_setupdata();
got_sud=FALSE;
}
if ( !(EP2468STAT & bmEP2EMPTY) ) {
printf ( "ep2 out received data\n" );
if ( !(EP2468STAT & bmEP6FULL) ) { // wait for at least one empty in buffer
WORD i;
printf ( "Sending data to ep6 in\n");
bytes = MAKEWORD(EP2BCH,EP2BCL);
for (i=0;i<bytes;++i) EP6FIFOBUF[i] = EP2FIFOBUF[i];
// can copy whole string w/ autoptr instead.
// or copy directly from one buf to another
// ARM ep6 out
EP6BCH=MSB(bytes);
SYNCDELAY;
EP6BCL=LSB(bytes);
REARM(); // ep2
//printf ( "Re-Armed ep2\n" );
}
}
}
}
// Called once at startup
//
void mainInit(void) {
xdata uint8 thisByte = 0xFF;
xdata uint16 blockSize;
setIntCount = 23;
// This is only necessary for cases where you want to load firmware into the RAM of an FX2 that
// has already loaded firmware from an EEPROM. It should definitely be removed for firmwares
// which are themselves to be loaded from EEPROM.
#ifndef EEPROM
RENUMERATE_UNCOND();
#endif
// Disable alternate functions for PORTA 0,1,3 & 7.
PORTACFG = 0x00;
// Return FIFO setings back to default just in case previous firmware messed with them.
SYNCDELAY; PINFLAGSAB = 0x00;
SYNCDELAY; PINFLAGSCD = 0x00;
SYNCDELAY; FIFOPINPOLAR = 0x00;
// Global settings
SYNCDELAY; REVCTL = (bmDYN_OUT | bmENH_PKT);
SYNCDELAY; CPUCS = bmCLKSPD1; // 48MHz
// Drive IFCLK at 48MHz, enable slave FIFOs
//SYNCDELAY; IFCONFIG = (bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmFIFOS);
SYNCDELAY; IFCONFIG = (bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmPORTS);
// EP4 & EP8 are unused
SYNCDELAY; EP4CFG = 0x00;
SYNCDELAY; EP8CFG = 0x00;
SYNCDELAY; EP4FIFOCFG = 0x00;
SYNCDELAY; EP8FIFOCFG = 0x00;
// EP1OUT & EP1IN
SYNCDELAY; EP1OUTCFG = (bmVALID | bmBULK);
SYNCDELAY; EP1INCFG = (bmVALID | bmBULK);
// EP2OUT & EP6IN are quad-buffered bulk endpoints
SYNCDELAY; EP2CFG = (bmVALID | bmBULK);
SYNCDELAY; EP6CFG = (bmVALID | bmBULK | bmDIR);
// Reset FIFOs for EP2OUT & EP6IN
SYNCDELAY; FIFORESET = bmNAKALL;
SYNCDELAY; FIFORESET = 2; // reset EP2OUT
SYNCDELAY; FIFORESET = 6; // reset EP6IN
SYNCDELAY; FIFORESET = 0x00;
// Arm EP1OUT
EP1OUTBC = 0x00;
// Arm the EP2OUT buffers. Done four times because it's quad-buffered
SYNCDELAY; OUTPKTEND = bmSKIP | 2; // EP2OUT
SYNCDELAY; OUTPKTEND = bmSKIP | 2;
SYNCDELAY; OUTPKTEND = bmSKIP | 2;
SYNCDELAY; OUTPKTEND = bmSKIP | 2;
// EP2OUT & EP6IN automatically commit packets
SYNCDELAY; EP2FIFOCFG = bmAUTOOUT;
SYNCDELAY; EP6FIFOCFG = bmAUTOIN;
// Auto-commit 512-byte packets from EP6IN (master may commit early by asserting PKTEND)
SYNCDELAY; EP6AUTOINLENH = 0x02;
SYNCDELAY; EP6AUTOINLENL = 0x00;
// Turbo I2C
I2CTL |= bm400KHZ;
// Auto-pointers
AUTOPTRSETUP = bmAPTREN | bmAPTR1INC | bmAPTR2INC;
// Port lines all inputs...
IOA = 0xFF;
OEA = 0x00;
IOB = 0xFF;
OEB = 0x00;
IOC = 0xFF;
OEC = 0x00;
IOD = 0xFF;
OED = 0x00;
IOE = 0xFF;
OEE = 0x00;
#ifdef EEPROM
#include "init.inc"
#endif
#ifdef DEBUG
usartInit();
usartSendString("MakeStuff FPGALink/FX2 v1.1\r");
#endif
}
// Called once at startup
//
void mainInit(void) {
__xdata uint8 thisByte = 0xFF;
__xdata uint16 blockSize;
// This is only necessary for cases where you want to load firmware into the RAM of an FX2 that
// has already loaded firmware from an EEPROM. It should definitely be removed for firmwares
// which are themselves to be loaded from EEPROM.
#ifndef EEPROM
RENUMERATE_UNCOND();
#endif
// Needs to be matched to stuff in HDMI2USB/cypress/hdmi2usb.c TD_Init
// void TD_Init(void) // Called once at startup
// Clear wakeup (see AN15813: http://www.cypress.com/?docID=4633)
WAKEUPCS = bmWU | bmDPEN | bmWUEN;
WAKEUPCS = bmWU | bmDPEN | bmWUEN;
// Disable alternate functions for PORTA 0,1,3 & 7.
PORTACFG = 0x00;
/*
// Return FIFO settings back to default just in case previous firmware messed with them.
SYNCDELAY; PINFLAGSAB = 0x00;
SYNCDELAY; PINFLAGSCD = 0x00;
SYNCDELAY; FIFOPINPOLAR = 0x00;
// Global settings
SYNCDELAY; REVCTL = (bmDYN_OUT | bmENH_PKT); // 0x03
SYNCDELAY; CPUCS = bmCLKSPD1; // 48MHz 0x10
// Drive IFCLK at 48MHz, enable slave FIFOs
//SYNCDELAY; IFCONFIG = (bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmFIFOS);
SYNCDELAY; IFCONFIG = (bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmPORTS); // 0xe0
// EP1OUT & EP1IN
SYNCDELAY; EP1OUTCFG = (bmVALID | bmBULK); // 0xa0
SYNCDELAY; EP1INCFG = (bmVALID | bmBULK); // 0xa0
// EP2OUT & EP6IN are quad-buffered bulk endpoints
SYNCDELAY; EP2CFG = (bmVALID | bmBULK); // 0xa0
SYNCDELAY; EP4CFG = 0x00;
SYNCDELAY; EP6CFG = (bmVALID | bmBULK | bmDIR); // 0xe0
SYNCDELAY; EP8CFG = 0x00;
// EP2OUT & EP6IN automatically commit packets
SYNCDELAY; EP2FIFOCFG = bmAUTOOUT; // 0x10
SYNCDELAY; EP4FIFOCFG = 0x00;
SYNCDELAY; EP6FIFOCFG = bmAUTOIN; // 0x08
SYNCDELAY; EP8FIFOCFG = 0x00;
// Reset FIFOs for EP2OUT & EP6IN
SYNCDELAY; FIFORESET = bmNAKALL; // 0x80
SYNCDELAY; FIFORESET = 2; // reset EP2OUT
SYNCDELAY; FIFORESET = 6; // reset EP6IN
SYNCDELAY; FIFORESET = 0x00;
// Arm EP1OUT
EP1OUTBC = 0x00;
// Arm the EP2OUT buffers. Done four times because it's quad-buffered
SYNCDELAY; OUTPKTEND = bmSKIP | 2; // EP2OUT 0x82
SYNCDELAY; OUTPKTEND = bmSKIP | 2;
SYNCDELAY; OUTPKTEND = bmSKIP | 2;
SYNCDELAY; OUTPKTEND = bmSKIP | 2;
// Auto-commit 512-byte packets from EP6IN (master may commit early by asserting PKTEND)
SYNCDELAY; EP6AUTOINLENH = 0x02;
SYNCDELAY; EP6AUTOINLENL = 0x00;
// Turbo I2C
I2CTL |= bm400KHZ;
// Auto-pointers
AUTOPTRSETUP = bmAPTREN | bmAPTR1INC | bmAPTR2INC; // 0x07
// Port lines all inputs...
IOA = 0xFF;
OEA = 0x00;
IOB = 0xFF;
OEB = 0x00;
IOC = 0xFF;
OEC = 0x00;
IOD = 0xFF;
OED = 0x00;
IOE = 0xFF;
OEE = 0x00;
#ifdef EEPROM
#ifdef BSP
#include STR(boards/BSP.c)
#endif
#endif
*/
I2CTL |= bm400KHZ;
TD_Init();
#ifdef DEBUG
usartInit();
{
const uint8 *s = dev_strings;
uint8 len;
s = s + *s;
len = (*s)/2 - 1;
s += 2;
while ( len ) {
usartSendByte(*s);
s += 2;
len--;
}
usartSendByte(' ');
len = (*s)/2 - 1;
s += 2;
while ( len ) {
usartSendByte(*s);
s += 2;
len--;
}
usartSendByte('\r');
}
#endif
}
// Called once at startup
//
void mainInit(void) {
xdata uint8 thisByte = 0xFF;
xdata uint16 blockSize;
// This is only necessary for cases where you want to load firmware into the RAM of an FX2 that
// has already loaded firmware from an EEPROM. It should definitely be removed for firmwares
// which are themselves to be loaded from EEPROM.
#ifndef EEPROM
RENUMERATE_UNCOND();
#endif
// Disable alternate functions for PORTA 0,1,3 & 7.
PORTACFG = 0x00;
// Return FIFO setings back to default just in case previous firmware messed with them.
SYNCDELAY; PINFLAGSAB = 0x00;
SYNCDELAY; PINFLAGSCD = 0x00;
SYNCDELAY; FIFOPINPOLAR = 0x00;
// Global settings
SYNCDELAY; REVCTL = (bmDYN_OUT | bmENH_PKT);
SYNCDELAY; CPUCS = bmCLKSPD1; // 48MHz
// Drive IFCLK at 48MHz, enable slave FIFOs
SYNCDELAY; IFCONFIG = (bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmFIFOS);
// EP4 & EP8 are unused
SYNCDELAY; EP4CFG = 0x00;
SYNCDELAY; EP8CFG = 0x00;
SYNCDELAY; EP4FIFOCFG = 0x00;
SYNCDELAY; EP8FIFOCFG = 0x00;
// EP1OUT & EP1IN
SYNCDELAY; EP1OUTCFG = (bmVALID | bmBULK);
SYNCDELAY; EP1INCFG = (bmVALID | bmBULK);
// EP2OUT & EP6IN are quad-buffered bulk endpoints
SYNCDELAY; EP2CFG = (bmVALID | bmBULK);
SYNCDELAY; EP6CFG = (bmVALID | bmBULK | bmDIR);
// Reset FIFOs for EP2OUT & EP6IN
SYNCDELAY; FIFORESET = bmNAKALL;
SYNCDELAY; FIFORESET = 2; // reset EP2OUT
SYNCDELAY; FIFORESET = 6; // reset EP6IN
SYNCDELAY; FIFORESET = 0x00;
// Arm EP1OUT
EP1OUTBC = 0x00;
// Arm the EP2OUT buffers. Done four times because it's quad-buffered
SYNCDELAY; OUTPKTEND = bmSKIP | 2; // EP2OUT
SYNCDELAY; OUTPKTEND = bmSKIP | 2;
SYNCDELAY; OUTPKTEND = bmSKIP | 2;
SYNCDELAY; OUTPKTEND = bmSKIP | 2;
// EP2OUT & EP6IN automatically commit packets
SYNCDELAY; EP2FIFOCFG = bmAUTOOUT;
SYNCDELAY; EP6FIFOCFG = bmAUTOIN;
// Auto-commit 512-byte packets from EP6IN (master may commit early by asserting PKTEND)
SYNCDELAY; EP6AUTOINLENH = 0x02;
SYNCDELAY; EP6AUTOINLENL = 0x00;
// Turbo I2C
I2CTL |= bm400KHZ;
// Auto-pointers
AUTOPTRSETUP = bmAPTREN | bmAPTR1INC | bmAPTR2INC;
// Port lines...
IOA = 0x00;
OEA = 0x00;
IOC = 0x00;
OEC = 0x00;
IOD = 0x00;
OED = 0x00;
IOE = 0x00;
OEE = 0x00;
// Disable JTAG mode by default (i.e don't drive JTAG pins)
jtagSetEnabled(false);
#ifdef BOOT
promStartRead(false, 0x0000);
if ( promPeekByte() == 0xC2 ) {
promNextByte(); // VID(L)
promNextByte(); // VID(H)
promNextByte(); // PID(L)
promNextByte(); // PID(H)
promNextByte(); // DID(L)
promNextByte(); // DID(H)
promNextByte(); // Config byte
promNextByte(); // Length(H)
thisByte = promPeekByte();
while ( !(thisByte & 0x80) ) {
blockSize = thisByte;
blockSize <<= 8;
promNextByte(); // Length(L)
blockSize |= promPeekByte();
blockSize += 2; // Space taken by address
while ( blockSize-- ) {
promNextByte();
}
promNextByte(); // Length(H)
thisByte = promPeekByte();
}
promNextByte(); // Length(L)
promNextByte(); // Address(H)
promNextByte(); // Address(L)
promNextByte(); // Last byte
promNextByte(); // First byte after the end of the firmware
}
jtagSetEnabled(true);
jtagCsvfInit();
m_diagnosticCode = jtagCsvfPlay();
jtagSetEnabled(false);
thisByte = promPeekByte();
promNextByte();
blockSize = promPeekByte();
promNextByte();
blockSize <<= 8;
blockSize |= promPeekByte();
promNextByte();
if ( thisByte ) {
if ( blockSize ) {
fifoSendPromData(0x10000UL + blockSize);
}
} else if ( blockSize ) {
fifoSendPromData(blockSize);
}
promStopRead();
USBCS &= ~bmDISCON;
#endif
#ifdef DEBUG
usartInit();
usartSendString("MakeStuff FPGALink/FX2 v1.1\r");
#endif
initPorts();
}
