void PINT_Deinit(PINT_Type *base)
{
uint32_t i;
assert(base);
/* Cleanup */
PINT_DisableCallback(base);
for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
{
s_pintCallback[i] = NULL;
}
#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1)
/* Reset the peripheral */
RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn);
/* Disable the peripheral clock */
CLOCK_DisableClock(kCLOCK_GpioInt);
#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0)
/* Reset the peripheral */
RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn);
/* Disable the peripheral clock */
CLOCK_DisableClock(kCLOCK_Gpio0);
#else
/* Reset the peripheral */
RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn);
/* Disable the peripheral clock */
CLOCK_DisableClock(kCLOCK_Pint);
#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */
}
void PINT_Init(PINT_Type *base)
{
uint32_t i;
uint32_t pmcfg;
assert(base);
pmcfg = 0;
for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
{
s_pintCallback[i] = NULL;
}
/* Disable all bit slices */
for (i = 0; i < PINT_PIN_INT_COUNT; i++)
{
pmcfg = pmcfg | (kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U)));
}
#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1)
/* Enable the peripheral clock */
CLOCK_EnableClock(kCLOCK_GpioInt);
/* Reset the peripheral */
RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn);
#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0)
/* Enable the peripheral clock */
CLOCK_EnableClock(kCLOCK_Gpio0);
/* Reset the peripheral */
RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn);
#else
/* Enable the peripheral clock */
CLOCK_EnableClock(kCLOCK_Pint);
/* Reset the peripheral */
RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn);
#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE && FSL_FEATURE_CLOCK_HAS_NO_GPIOINT_CLOCK_SOURCE*/
/* Disable all pattern match bit slices */
base->PMCFG = pmcfg;
}
/* Initialize debug console. */
status_t BOARD_InitDebugConsole(void)
{
status_t result;
/* attach 12 MHz clock to FLEXCOMM0 (debug console) */
CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
RESET_PeripheralReset(BOARD_DEBUG_UART_RST);
// result = DbgConsole_Init(BOARD_DEBUG_UART_BASEADDR, BOARD_DEBUG_UART_BAUDRATE, DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM,
// BOARD_DEBUG_UART_CLK_FREQ);
assert(kStatus_Success == result);
return result;
}
/*!
* brief Initializes the GPIO peripheral.
*
* This function ungates the GPIO clock.
*
* param base GPIO peripheral base pointer.
* param port GPIO port number.
*/
void GPIO_PortInit(GPIO_Type *base, uint32_t port)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
assert(port < ARRAY_SIZE(s_gpioClockName));
/* Upgate the GPIO clock */
CLOCK_EnableClock(s_gpioClockName[port]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET)
/* Reset the GPIO module */
RESET_PeripheralReset(s_gpioResets[port]);
#endif
}
void MRT_Init(MRT_Type *base, const mrt_config_t *config)
{
assert(config);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Ungate the MRT clock */
CLOCK_EnableClock(s_mrtClocks[MRT_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* Reset the module */
RESET_PeripheralReset(s_mrtResets[MRT_GetInstance(base)]);
/* Set timer operating mode */
base->MODCFG = MRT_MODCFG_MULTITASK(config->enableMultiTask);
}
void GINT_Init(GINT_Type *base)
{
uint32_t instance;
instance = GINT_GetInstance(base);
s_gintCallback[instance] = NULL;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Enable the peripheral clock */
CLOCK_EnableClock(s_gintClocks[instance]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* Reset the peripheral */
RESET_PeripheralReset(s_gintResets[instance]);
}
void DMIC_Init(DMIC_Type *base)
{
assert(base);
/* Enable the clock to the register interface */
CLOCK_EnableClock(s_dmicClock[DMIC_GetInstance(base)]);
/* Reset the peripheral */
RESET_PeripheralReset(kDMIC_RST_SHIFT_RSTn);
/* Disable DMA request*/
base->CHANNEL[0].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_DMAEN(1);
base->CHANNEL[1].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_DMAEN(1);
/* Disable DMIC interrupt. */
base->CHANNEL[0].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_INTEN(1);
base->CHANNEL[1].FIFO_CTRL &= ~DMIC_CHANNEL_FIFO_CTRL_INTEN(1);
}
void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config)
{
assert(config);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Enable the timer clock*/
CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* Reset the module */
RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]);
/* Setup the cimer mode and count select */
base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input);
/* Setup the timer prescale value */
base->PR = CTIMER_PR_PRVAL(config->prescale);
}
void spi_format(spi_t *obj, int bits, int mode, int slave)
{
spi_master_config_t master_config;
spi_slave_config_t slave_config;
/* Bits: values between 4 and 16 are valid */
MBED_ASSERT(bits >= 4 && bits <= 16);
obj->bits = bits;
if (slave) {
/* Slave config */
SPI_SlaveGetDefaultConfig(&slave_config);
slave_config.dataWidth = (spi_data_width_t)(bits - 1);
slave_config.polarity = (mode & 0x2) ? kSPI_ClockPolarityActiveLow : kSPI_ClockPolarityActiveHigh;
slave_config.phase = (mode & 0x1) ? kSPI_ClockPhaseSecondEdge : kSPI_ClockPhaseFirstEdge;
SPI_SlaveInit(spi_address[obj->instance], &slave_config);
} else {
/* Master config */
SPI_MasterGetDefaultConfig(&master_config);
master_config.dataWidth = (spi_data_width_t)(bits - 1);
master_config.polarity = (mode & 0x2) ? kSPI_ClockPolarityActiveLow : kSPI_ClockPolarityActiveHigh;
master_config.phase = (mode & 0x1) ? kSPI_ClockPhaseSecondEdge : kSPI_ClockPhaseFirstEdge;
master_config.direction = kSPI_MsbFirst;
switch (obj->instance) {
case 0:
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0);
RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn);
break;
case 1:
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM1);
RESET_PeripheralReset(kFC1_RST_SHIFT_RSTn);
break;
case 2:
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2);
RESET_PeripheralReset(kFC2_RST_SHIFT_RSTn);
break;
case 3:
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM3);
RESET_PeripheralReset(kFC3_RST_SHIFT_RSTn);
break;
case 4:
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
RESET_PeripheralReset(kFC4_RST_SHIFT_RSTn);
break;
case 5:
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM5);
RESET_PeripheralReset(kFC5_RST_SHIFT_RSTn);
break;
case 6:
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM6);
RESET_PeripheralReset(kFC6_RST_SHIFT_RSTn);
break;
case 7:
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM7);
RESET_PeripheralReset(kFC7_RST_SHIFT_RSTn);
break;
#if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 8U)
case 8:
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM8);
RESET_PeripheralReset(kFC8_RST_SHIFT_RSTn);
break;
#endif
#if (FSL_FEATURE_SOC_FLEXCOMM_COUNT > 9U)
case 9:
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM9);
RESET_PeripheralReset(kFC9_RST_SHIFT_RSTn);
break;
#endif
}
SPI_MasterInit(spi_address[obj->instance], &master_config, 12000000);
}
}
status_t LCDC_Init(LCD_Type *base, const lcdc_config_t *config, uint32_t srcClock_Hz)
{
assert(config);
assert(srcClock_Hz);
assert((config->ppl & 0xFU) == 0U);
assert((config->upperPanelAddr & 0x07U) == 0U);
assert((config->lowerPanelAddr & 0x07U) == 0U);
uint32_t reg;
uint32_t divider;
uint32_t instance;
/* Verify the clock here. */
if (!LCDC_GetClockDivider(config, srcClock_Hz, ÷r))
{
return kStatus_InvalidArgument;
}
instance = LCDC_GetInstance(base);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
CLOCK_EnableClock(s_lcdClocks[instance]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* Reset the module */
RESET_PeripheralReset(s_lcdResets[instance]);
/* Set register CTRL. */
reg = base->CTRL & (LCD_CTRL_LCDVCOMP_MASK | LCD_CTRL_WATERMARK_MASK);
reg |= (uint32_t)(config->dataFormat) | (uint32_t)(config->display) | LCD_CTRL_LCDBPP(config->bpp);
if (config->swapRedBlue)
{
reg |= LCD_CTRL_BGR_MASK;
}
base->CTRL = reg;
/* Clean pending interrupts and disable all interrupts. */
base->INTCLR = LCDC_NORMAL_INT_MASK;
base->CRSR_INTCLR = LCDC_CURSOR_INT_MASK;
base->INTMSK = 0U;
base->CRSR_INTMSK = 0U;
/* Configure timing. */
base->TIMH = LCD_TIMH_PPL((config->ppl / 16U) - 1U) | LCD_TIMH_HSW(config->hsw - 1U) |
LCD_TIMH_HFP(config->hfp - 1U) | LCD_TIMH_HBP(config->hbp - 1U);
base->TIMV = LCD_TIMV_LPP(config->lpp - 1U) | LCD_TIMV_VSW(config->vsw - 1U) | LCD_TIMV_VFP(config->vfp - 1U) |
LCD_TIMV_VBP(config->vbp - 1U);
base->POL = (uint32_t)(config->polarityFlags) | LCD_POL_ACB(config->acBiasFreq - 1U) | divider;
/* Line end configuration. */
if (config->enableLineEnd)
{
base->LE = LCD_LE_LED(config->lineEndDelay - 1U) | LCD_LE_LEE_MASK;
}
else
{
base->LE = 0U;
}
/* Set panel frame base address. */
base->UPBASE = config->upperPanelAddr;
base->LPBASE = config->lowerPanelAddr;
return kStatus_Success;
}
