static void riscv_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); cpu_reset(cs); qemu_init_vcpu(cs); mcc->parent_realize(dev, errp); }
static void riscv_cpu_reset(CPUState *s) { RISCVCPU *cpu = RISCV_CPU(s); RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); CPURISCVState *env = &cpu->env; mcc->parent_reset(s); tlb_flush(s, 1); cpu_state_reset(env); }
static void riscv_cpu_reset(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs); RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); CPURISCVState *env = &cpu->env; mcc->parent_reset(cs); #ifndef CONFIG_USER_ONLY env->priv = PRV_M; env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); env->mcause = 0; env->pc = env->resetvec; #endif cs->exception_index = EXCP_NONE; set_default_nan_mode(1, &env->fp_status); }
static void riscv_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); Error *local_err = NULL; cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); return; } riscv_cpu_register_gdb_regs_for_features(cs); qemu_init_vcpu(cs); cpu_reset(cs); mcc->parent_realize(dev, errp); }