static tBoolean
WaitI2CFinished(void)
{
//
// Wait until the current byte has been transferred.
//
while(ROM_I2CMasterIntStatus(I2C0_MASTER_BASE, false) == 0)
{
}
if(I2CMasterErr(I2C0_MASTER_BASE) != I2C_MASTER_ERR_NONE)
{
ROM_I2CMasterIntClear(I2C0_MASTER_BASE);
return(false);
}
//
// Clear any interrupts set.
//
while(ROM_I2CMasterIntStatus(I2C0_MASTER_BASE, false))
{
ROM_I2CMasterIntClear(I2C0_MASTER_BASE);
}
return(true);
}
int I2CRead(unsigned char slave, unsigned char address, unsigned int len, unsigned char * readdata, unsigned int readcnt)
{
unsigned long ulToRead;
// Start with a dummy write to get the address set in the EEPROM.
ROM_I2CMasterSlaveAddrSet(I2C_MASTER_BASE, slave, false);
// Place the address to be written in the data register.
ROM_I2CMasterDataPut(I2C_MASTER_BASE, address);
// Perform a single send, writing the address as the only byte.
ROM_I2CMasterControl(I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_START);
// Wait until the current byte has been transferred.
if(!WaitI2CFinished())
{
return(false);
}
// Put the I2C master into receive mode.
ROM_I2CMasterSlaveAddrSet(I2C_MASTER_BASE, slave, true);
// Start the receive.
ROM_I2CMasterControl(I2C_MASTER_BASE, ((readcnt > 1) ? I2C_MASTER_CMD_BURST_RECEIVE_START :
I2C_MASTER_CMD_SINGLE_RECEIVE));
// Receive the required number of bytes.
ulToRead = readcnt;
while(ulToRead)
{
// Wait until the current byte has been read.
while(ROM_I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0){}
// Fixes I2C transactions.. ?
ROM_SysCtlDelay(1000);
// Clear pending interrupt notification.
ROM_I2CMasterIntClear(I2C_MASTER_BASE);
// Read the received character.
*readdata++ = ROM_I2CMasterDataGet(I2C_MASTER_BASE);
ulToRead--;
// Set up for the next byte if any more remain.
if(ulToRead)
{
ROM_I2CMasterControl(I2C_MASTER_BASE, ((ulToRead == 1) ? I2C_MASTER_CMD_BURST_RECEIVE_FINISH :
I2C_MASTER_CMD_BURST_RECEIVE_CONT));
}
}
return(readcnt - ulToRead);
}
static tBoolean WaitI2CFinished(void)
{
// Wait until the current byte has been transferred.
while(ROM_I2CMasterIntStatus(I2C_MASTER_BASE, false) == 0){}
if(ROM_I2CMasterErr(I2C_MASTER_BASE) != I2C_MASTER_ERR_NONE)
{
ROM_I2CMasterIntClear(I2C_MASTER_BASE);
return(false);
}
// Clear any interrupts set.
while(ROM_I2CMasterIntStatus(I2C_MASTER_BASE, false))
{
ROM_I2CMasterIntClear(I2C_MASTER_BASE);
}
// Fixes I2C transactions.. ?
ROM_SysCtlDelay(10000);
return(true);
}
void i2cman_handler()
{
ROM_I2CMasterIntClear(I2C_PORT);
if(current_op == end || current_op == 0)
return; // do absolutely nothing (irq may be called after aborting)
uint32_t error = finish_op(current_op);
if(error != I2C_MASTER_ERR_NONE)
{
stop();
if(error & I2C_MASTER_ERR_ARB_LOST)
{
if(error_func)
error_func(I2C_ARBLOST);
}
else
{
// error, abort completely
//kill_op(current_op);
// bad bad bad!
if(error_func)
error_func(I2C_NOACK);
}
return;
}
current_op ++;
if(current_op == end)
{
stop(); // all done
if(success_func)
success_func();
return;
}
// otherwise, process the next op
start_op(current_op);
}
void I2C0IntHandler(void)
{
statearray[stateindex++] = g_ulState;
if (stateindex == 20)
stateindex = 0;
//
// Clear the I2C interrupt.
//
ROM_I2CMasterIntClear(I2C0_MASTER_BASE);
//
// Determine what to do based on the current state.
//
switch(g_ulState)
{
//
// The idle state.
//
case STATE_IDLE:
{
//
// There is nothing to be done.
//
break;
}
//
// The state for the middle of a burst write.
//
case STATE_WRITE_NEXT:
{
//
// Write the next byte to the data register.
//
ROM_I2CMasterDataPut(I2C0_MASTER_BASE, *g_pucData++);
g_ulCount--;
//
// Continue the burst write.
//
ROM_I2CMasterControl(I2C0_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_CONT);
//
// If there is one byte left, set the next state to the final write
// state.
//
if(g_ulCount == 1)
{
g_ulState = STATE_WRITE_FINAL;
}
//
// This state is done.
//
break;
}
//
// The state for the final write of a burst sequence.
//
case STATE_WRITE_FINAL:
{
//
// Write the final byte to the data register.
//
ROM_I2CMasterDataPut(I2C0_MASTER_BASE, *g_pucData++);
g_ulCount--;
//
// Finish the burst write.
//
ROM_I2CMasterControl(I2C0_MASTER_BASE,
I2C_MASTER_CMD_BURST_SEND_FINISH);
//
// The next state is to wait for the burst write to complete.
//
g_ulState = STATE_SEND_ACK;
//
// This state is done.
//
break;
}
//
// Wait for an ACK on the read after a write.
//
case STATE_WAIT_ACK:
{
//
// See if there was an error on the previously issued read.
//
if(ROM_I2CMasterErr(I2C0_MASTER_BASE) == I2C_MASTER_ERR_NONE)
{
//
// Read the byte received.
//
ROM_I2CMasterDataGet(I2C0_MASTER_BASE);
//
// There was no error, so the state machine is now idle.
//
g_ulState = STATE_IDLE;
//
// This state is done.
//
break;
}
else
{
//
// Fall through to STATE_SEND_ACK.
//
BBLedToggle();
}
}
//
// Send a read request, looking for the ACK to indicate that the write
// is done.
//
case STATE_SEND_ACK:
{
//
// Put the I2C master into receive mode.
//
ROM_I2CMasterSlaveAddrSet(I2C0_MASTER_BASE, currentaddress, true);
//
// Perform a single byte read.
//
ROM_I2CMasterControl(I2C0_MASTER_BASE, I2C_MASTER_CMD_SINGLE_RECEIVE);
//
// The next state is the wait for the ack.
//
g_ulState = STATE_WAIT_ACK;
//
// This state is done.
//
break;
}
//
// The state for a single byte read.
//
case STATE_READ_ONE:
{
//
// Put the I2C master into receive mode.
//
ROM_I2CMasterSlaveAddrSet(I2C0_MASTER_BASE, currentaddress, true);
//
// Perform a single byte read.
//
ROM_I2CMasterControl(I2C0_MASTER_BASE, I2C_MASTER_CMD_SINGLE_RECEIVE);
//
// The next state is the wait for final read state.
//
g_ulState = STATE_READ_WAIT;
//
// This state is done.
//
break;
}
//
// The state for the start of a burst read.
//
case STATE_READ_FIRST: // 6
{
//
// Put the I2C master into receive mode.
//
ROM_I2CMasterSlaveAddrSet(I2C0_MASTER_BASE, currentaddress, true);
//
// Start the burst receive.
//
ROM_I2CMasterControl(I2C0_MASTER_BASE,
I2C_MASTER_CMD_BURST_RECEIVE_START);
//
// The next state is the middle of the burst read.
//
g_ulState = STATE_READ_NEXT; // 7
//
// This state is done.
//
break;
}
//
// The state for the middle of a burst read.
//
case STATE_READ_NEXT: // 7
{
//
// Read the received character.
//
*g_pucData++ = ROM_I2CMasterDataGet(I2C0_MASTER_BASE);
g_ulCount--;
//
// Continue the burst read.
//
ROM_I2CMasterControl(I2C0_MASTER_BASE,
I2C_MASTER_CMD_BURST_RECEIVE_CONT);
//
// If there are two characters left to be read, make the next
// state be the end of burst read state.
//
if(g_ulCount == 2)
{
g_ulState = STATE_READ_FINAL; // 8
}
//
// This state is done.
//
break;
}
//
// The state for the end of a burst read.
//
case STATE_READ_FINAL: // 8
{
//
// Read the received character.
//
*g_pucData++ = ROM_I2CMasterDataGet(I2C0_MASTER_BASE);
g_ulCount--;
//
// Finish the burst read.
//
ROM_I2CMasterControl(I2C0_MASTER_BASE,
I2C_MASTER_CMD_BURST_RECEIVE_FINISH);
//
// The next state is the wait for final read state.
//
g_ulState = STATE_READ_WAIT; // 9
//
// This state is done.
//
break;
}
//
// This state is for the final read of a single or burst read.
//
case STATE_READ_WAIT: // 9
{
//
// Read the received character.
//
tempc = ROM_I2CMasterDataGet(I2C0_MASTER_BASE);
*g_pucData++ = (unsigned char)tempc;
g_ulCount--;
//
// The state machine is now idle.
//
g_ulState = STATE_IDLE;
//
// This state is done.
//
break;
}
}
}
//*****************************************************************************
//
// Writes a register in the TLV320AIC3107 DAC.
//
// \param ucRegister is the offset to the register to write.
// \param ulData is the data to be written to the DAC register.
//
// This function will write the register passed in ucAddr with the value
// passed in to ulData. The data in ulData is actually 9 bits and the
// value in ucAddr is interpreted as 7 bits.
//
// \return True on success or false on error.
//
//*****************************************************************************
static tBoolean
DACWriteRegister(unsigned char ucRegister, unsigned long ulData)
{
//
// Set the slave address.
//
ROM_I2CMasterSlaveAddrSet(DAC_I2C_MASTER_BASE, TI_TLV320AIC3107_ADDR,
false);
//
// Write the first byte to the controller (register)
//
ROM_I2CMasterDataPut(DAC_I2C_MASTER_BASE, ucRegister);
//
// Continue the transfer.
//
ROM_I2CMasterControl(DAC_I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_START);
//
// Wait until the current byte has been transferred.
//
while(ROM_I2CMasterIntStatus(DAC_I2C_MASTER_BASE, false) == 0)
{
}
if(ROM_I2CMasterErr(DAC_I2C_MASTER_BASE) != I2C_MASTER_ERR_NONE)
{
ROM_I2CMasterIntClear(DAC_I2C_MASTER_BASE);
return(false);
}
//
// Wait until the current byte has been transferred.
//
while(ROM_I2CMasterIntStatus(DAC_I2C_MASTER_BASE, false))
{
ROM_I2CMasterIntClear(DAC_I2C_MASTER_BASE);
}
//
// Write the data byte to the controller.
//
ROM_I2CMasterDataPut(DAC_I2C_MASTER_BASE, ulData);
//
// End the transfer.
//
ROM_I2CMasterControl(DAC_I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_FINISH);
//
// Wait until the current byte has been transferred.
//
while(ROM_I2CMasterIntStatus(DAC_I2C_MASTER_BASE, false) == 0)
{
}
if(ROM_I2CMasterErr(DAC_I2C_MASTER_BASE) != I2C_MASTER_ERR_NONE)
{
return(false);
}
while(ROM_I2CMasterIntStatus(DAC_I2C_MASTER_BASE, false))
{
ROM_I2CMasterIntClear(DAC_I2C_MASTER_BASE);
}
return(true);
}
//*****************************************************************************
//
// Reads a register in the TLV320AIC3107 DAC.
//
// \param ucRegister is the offset to the register to write.
// \param pucData is a pointer to the returned data.
//
// \return \b true on success or \b false on error.
//
//*****************************************************************************
static tBoolean
DACReadRegister(unsigned char ucRegister, unsigned char *pucData)
{
//
// Set the slave address and "WRITE"
//
ROM_I2CMasterSlaveAddrSet(DAC_I2C_MASTER_BASE, TI_TLV320AIC3107_ADDR,
false);
//
// Write the first byte to the controller (register)
//
ROM_I2CMasterDataPut(DAC_I2C_MASTER_BASE, ucRegister);
//
// Continue the transfer.
//
ROM_I2CMasterControl(DAC_I2C_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_START);
//
// Wait until the current byte has been transferred.
//
while(ROM_I2CMasterIntStatus(DAC_I2C_MASTER_BASE, false) == 0)
{
}
if(ROM_I2CMasterErr(DAC_I2C_MASTER_BASE) != I2C_MASTER_ERR_NONE)
{
ROM_I2CMasterIntClear(DAC_I2C_MASTER_BASE);
return(false);
}
//
// Wait until the current byte has been transferred.
//
while(ROM_I2CMasterIntStatus(DAC_I2C_MASTER_BASE, false))
{
ROM_I2CMasterIntClear(DAC_I2C_MASTER_BASE);
}
//
// Set the slave address and "READ"/true.
//
ROM_I2CMasterSlaveAddrSet(DAC_I2C_MASTER_BASE, TI_TLV320AIC3107_ADDR, true);
//
// Read Data Byte.
//
ROM_I2CMasterControl(DAC_I2C_MASTER_BASE, I2C_MASTER_CMD_SINGLE_RECEIVE);
//
// Wait until the current byte has been transferred.
//
while(ROM_I2CMasterIntStatus(DAC_I2C_MASTER_BASE, false) == 0)
{
}
if(ROM_I2CMasterErr(DAC_I2C_MASTER_BASE) != I2C_MASTER_ERR_NONE)
{
ROM_I2CMasterIntClear(DAC_I2C_MASTER_BASE);
return(false);
}
//
// Wait until the current byte has been transferred.
//
while(ROM_I2CMasterIntStatus(DAC_I2C_MASTER_BASE, false))
{
ROM_I2CMasterIntClear(DAC_I2C_MASTER_BASE);
}
//
// Read the value received.
//
*pucData = ROM_I2CMasterDataGet(DAC_I2C_MASTER_BASE);
return(true);
}
//*****************************************************************************
//
// Reads from the I2C-attached EEPROM device.
//
// \param pucData points to storage for the data read from the EEPROM.
// \param ulOffset is the EEPROM address of the first byte to read.
// \param ulCount is the number of bytes of data to read from the EEPROM.
//
// This function reads one or more bytes of data from a given address in the
// ID EEPROM found on several of the development kit daughter boards. The
// return code indicates whether the read was successful.
//
// \return Returns \b true on success of \b false on failure.
//
//*****************************************************************************
static tBoolean
EEPROMReadPolled(unsigned char *pucData, unsigned long ulOffset,
unsigned long ulCount)
{
unsigned long ulToRead;
//
// Clear any previously signalled interrupts.
//
ROM_I2CMasterIntClear(I2C0_MASTER_BASE);
//
// Start with a dummy write to get the address set in the EEPROM.
//
ROM_I2CMasterSlaveAddrSet(I2C0_MASTER_BASE, ID_I2C_ADDR, false);
//
// Place the address to be written in the data register.
//
ROM_I2CMasterDataPut(I2C0_MASTER_BASE, ulOffset);
//
// Perform a single send, writing the address as the only byte.
//
ROM_I2CMasterControl(I2C0_MASTER_BASE, I2C_MASTER_CMD_BURST_SEND_START);
//
// Wait until the current byte has been transferred.
//
if(!WaitI2CFinished())
{
return(false);
}
//
// Put the I2C master into receive mode.
//
ROM_I2CMasterSlaveAddrSet(I2C0_MASTER_BASE, ID_I2C_ADDR, true);
//
// Start the receive.
//
ROM_I2CMasterControl(I2C0_MASTER_BASE,
((ulCount > 1) ? I2C_MASTER_CMD_BURST_RECEIVE_START :
I2C_MASTER_CMD_SINGLE_RECEIVE));
//
// Receive the required number of bytes.
//
ulToRead = ulCount;
while(ulToRead)
{
//
// Wait until the current byte has been read.
//
while(ROM_I2CMasterIntStatus(I2C0_MASTER_BASE, false) == 0)
{
}
//
// Clear pending interrupt notification.
//
ROM_I2CMasterIntClear(I2C0_MASTER_BASE);
//
// Read the received character.
//
*pucData++ = ROM_I2CMasterDataGet(I2C0_MASTER_BASE);
ulToRead--;
//
// Set up for the next byte if any more remain.
//
if(ulToRead)
{
ROM_I2CMasterControl(I2C0_MASTER_BASE,
((ulToRead == 1) ?
I2C_MASTER_CMD_BURST_RECEIVE_FINISH :
I2C_MASTER_CMD_BURST_RECEIVE_CONT));
}
}
//
// Tell the caller we read the required data.
//
return(true);
}
