void rtl8723e_dm_bt_reject_ap_aggregated_packet(struct ieee80211_hw *hw, bool b_reject)
{
#if 0
struct rtl_priv rtlpriv = rtl_priv(hw);
PRX_TS_RECORD pRxTs = NULL;
if(b_reject){
// Do not allow receiving A-MPDU aggregation.
if (rtlpriv->mac80211.vendor == PEER_CISCO) {
if (pHTInfo->bAcceptAddbaReq) {
RTPRINT(FBT, BT_TRACE, ("BT_Disallow AMPDU \n"));
pHTInfo->bAcceptAddbaReq = FALSE;
if(GetTs(Adapter, (PTS_COMMON_INFO*)(&pRxTs), pMgntInfo->Bssid, 0, RX_DIR, FALSE))
TsInitDelBA(Adapter, (PTS_COMMON_INFO)pRxTs, RX_DIR);
}
} else {
if (!pHTInfo->bAcceptAddbaReq) {
RTPRINT(FBT, BT_TRACE, ("BT_Allow AMPDU BT Idle\n"));
pHTInfo->bAcceptAddbaReq = TRUE;
}
}
} else {
if(rtlpriv->mac80211.vendor == PEER_CISCO) {
if (!pHTInfo->bAcceptAddbaReq) {
RTPRINT(FBT, BT_TRACE, ("BT_Allow AMPDU \n"));
pHTInfo->bAcceptAddbaReq = TRUE;
}
}
}
#endif
}
void writeOFDMPowerReg(
struct net_device* dev,
u8 index,
u32* pValue
)
{
struct r8192_priv *priv = rtllib_priv(dev);
u16 RegOffset_A[6] = { rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24,
rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04,
rTxAGC_A_Mcs11_Mcs08, rTxAGC_A_Mcs15_Mcs12};
u16 RegOffset_B[6] = { rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24,
rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04,
rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12};
u8 i, rf, pwr_val[4];
u32 writeVal;
u16 RegOffset;
for(rf=0; rf<2; rf++)
{
writeVal = pValue[rf];
for(i=0; i<4; i++)
{
pwr_val[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8));
if (pwr_val[i] > RF6052_MAX_TX_PWR)
pwr_val[i] = RF6052_MAX_TX_PWR;
}
writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) |(pwr_val[1]<<8) |pwr_val[0];
if(rf == 0)
RegOffset = RegOffset_A[index];
else
RegOffset = RegOffset_B[index];
PHY_SetBBReg(dev, RegOffset, bMaskDWord, writeVal);
RTPRINT(FPHY, PHY_TXPWR, ("Set 0x%x = %08x\n", RegOffset, writeVal));
if(((priv->rf_type == RF_2T2R) &&
(RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs15_Mcs12))||
((priv->rf_type != RF_2T2R) &&
(RegOffset == rTxAGC_A_Mcs07_Mcs04 || RegOffset == rTxAGC_B_Mcs07_Mcs04)) )
{
writeVal = pwr_val[3];
if(RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_A_Mcs07_Mcs04)
RegOffset = 0xc90;
if(RegOffset == rTxAGC_B_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs07_Mcs04)
RegOffset = 0xc98;
for(i=0; i<3; i++)
{
if(i!=2)
writeVal = (writeVal>8)?(writeVal-8):0;
else
writeVal = (writeVal>6)?(writeVal-6):0;
write_nic_byte(dev, (u32)(RegOffset+i), (u8)writeVal);
}
}
}
}
VOID
phy_PathAStandBy(
IN PADAPTER pAdapter
)
{
RTPRINT(FINIT, INIT_IQK, ("Path-A standby mode!\n"));
PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x0);
PHY_SetBBReg(pAdapter, 0x840, bMaskDWord, 0x00010000);
PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x80800000);
}
static void rtl8723e_phy_get_power_base( struct ieee80211_hw *hw,
u8 *ppowerlevel, u8 channel,
u32 *ofdmbase, u32 *mcsbase )
{
struct rtl_priv *rtlpriv = rtl_priv( hw );
struct rtl_phy *rtlphy = &rtlpriv->phy;
struct rtl_efuse *rtlefuse = rtl_efuse( rtl_priv( hw ) );
u32 powerbase0, powerbase1;
u8 legacy_pwrdiff, ht20_pwrdiff;
u8 i, powerlevel[2];
for ( i = 0; i < 2; i++ ) {
powerlevel[i] = ppowerlevel[i];
legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff[i][channel - 1];
powerbase0 = powerlevel[i] + legacy_pwrdiff;
powerbase0 = ( powerbase0 << 24 ) | ( powerbase0 << 16 ) |
( powerbase0 << 8 ) | powerbase0;
*( ofdmbase + i ) = powerbase0;
RTPRINT( rtlpriv, FPHY, PHY_TXPWR,
" [OFDM power base index rf(%c) = 0x%x]\n",
( ( i == 0 ) ? 'A' : 'B' ), *( ofdmbase + i ) );
}
for ( i = 0; i < 2; i++ ) {
if ( rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ) {
ht20_pwrdiff =
rtlefuse->txpwr_ht20diff[i][channel - 1];
powerlevel[i] += ht20_pwrdiff;
}
powerbase1 = powerlevel[i];
powerbase1 = ( powerbase1 << 24 ) |
( powerbase1 << 16 ) | ( powerbase1 << 8 ) | powerbase1;
*( mcsbase + i ) = powerbase1;
RTPRINT( rtlpriv, FPHY, PHY_TXPWR,
" [MCS power base index rf(%c) = 0x%x]\n",
( ( i == 0 ) ? 'A' : 'B' ), *( mcsbase + i ) );
}
}
static void rtl8723be_phy_get_power_base( struct ieee80211_hw *hw,
u8 *ppowerlevel_ofdm,
u8 *ppowerlevel_bw20,
u8 *ppowerlevel_bw40,
u8 channel, u32 *ofdmbase,
u32 *mcsbase )
{
struct rtl_priv *rtlpriv = rtl_priv( hw );
struct rtl_phy *rtlphy = &( rtlpriv->phy );
u32 powerbase0, powerbase1;
u8 i, powerlevel[2];
for ( i = 0; i < 2; i++ ) {
powerbase0 = ppowerlevel_ofdm[i];
powerbase0 = ( powerbase0 << 24 ) | ( powerbase0 << 16 ) |
( powerbase0 << 8 ) | powerbase0;
*( ofdmbase + i ) = powerbase0;
RTPRINT( rtlpriv, FPHY, PHY_TXPWR,
" [OFDM power base index rf(%c) = 0x%x]\n",
( ( i == 0 ) ? 'A' : 'B' ), *( ofdmbase + i ) );
}
for ( i = 0; i < 2; i++ ) {
if ( rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 )
powerlevel[i] = ppowerlevel_bw20[i];
else
powerlevel[i] = ppowerlevel_bw40[i];
powerbase1 = powerlevel[i];
powerbase1 = ( powerbase1 << 24 ) | ( powerbase1 << 16 ) |
( powerbase1 << 8 ) | powerbase1;
*( mcsbase + i ) = powerbase1;
RTPRINT( rtlpriv, FPHY, PHY_TXPWR,
" [MCS power base index rf(%c) = 0x%x]\n",
( ( i == 0 ) ? 'A' : 'B' ), *( mcsbase + i ) );
}
}
void getPowerBase(
struct net_device* dev,
u8* pPowerLevel,
u8 Channel,
u32* OfdmBase,
u32* MCSBase
)
{
struct r8192_priv *priv = rtllib_priv(dev);
u32 powerBase0, powerBase1;
u8 Legacy_pwrdiff=0, HT20_pwrdiff=0;
u8 i, powerlevel[2];
for(i=0; i<2; i++)
{
powerlevel[i] = pPowerLevel[i];
Legacy_pwrdiff = priv->TxPwrLegacyHtDiff[i][Channel-1];
powerBase0 = powerlevel[i] + Legacy_pwrdiff;
powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
*(OfdmBase+i) = powerBase0;
RTPRINT(FPHY, PHY_TXPWR, (" [OFDM power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(OfdmBase+i)));
}
for(i=0; i<2; i++)
{
if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
{
HT20_pwrdiff = priv->TxPwrHt20Diff[i][Channel-1];
powerlevel[i] += HT20_pwrdiff;
}
powerBase1 = powerlevel[i];
powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
*(MCSBase+i) = powerBase1;
RTPRINT(FPHY, PHY_TXPWR, (" [MCS power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(MCSBase+i)));
}
}
static void _rtl8723be_write_ofdm_power_reg( struct ieee80211_hw *hw,
u8 index, u32 *pvalue )
{
struct rtl_priv *rtlpriv = rtl_priv( hw );
u16 regoffset_a[6] = {
RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24,
RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
};
u16 regoffset_b[6] = {
RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24,
RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
};
u8 i, rf, pwr_val[4];
u32 writeval;
u16 regoffset;
for ( rf = 0; rf < 2; rf++ ) {
writeval = pvalue[rf];
for ( i = 0; i < 4; i++ ) {
pwr_val[i] = ( u8 )( ( writeval & ( 0x7f <<
( i * 8 ) ) ) >> ( i * 8 ) );
if ( pwr_val[i] > RF6052_MAX_TX_PWR )
pwr_val[i] = RF6052_MAX_TX_PWR;
}
writeval = ( pwr_val[3] << 24 ) | ( pwr_val[2] << 16 ) |
( pwr_val[1] << 8 ) | pwr_val[0];
if ( rf == 0 )
regoffset = regoffset_a[index];
else
regoffset = regoffset_b[index];
rtl_set_bbreg( hw, regoffset, MASKDWORD, writeval );
RTPRINT( rtlpriv, FPHY, PHY_TXPWR,
"Set 0x%x = %08x\n", regoffset, writeval );
}
}
u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
phy_PathA_IQK_8192C(
IN PADAPTER pAdapter,
IN BOOLEAN configPathB
)
{
u4Byte regEAC, regE94, regE9C, regEA4;
u1Byte result = 0x00;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
RTPRINT(FINIT, INIT_IQK, ("Path A IQK!\n"));
//path-A IQK setting
RTPRINT(FINIT, INIT_IQK, ("Path-A IQK setting!\n"));
if(pAdapter->interfaceIndex == 0)
{
PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
}
else
{
PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x10008c22);
PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x10008c22);
}
PHY_SetBBReg(pAdapter, rTx_IQK_PI_A, bMaskDWord, 0x82140102);
PHY_SetBBReg(pAdapter, rRx_IQK_PI_A, bMaskDWord, configPathB ? 0x28160202 :
IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202:0x28160502);
//path-B IQK setting
if(configPathB)
{
PHY_SetBBReg(pAdapter, rTx_IQK_Tone_B, bMaskDWord, 0x10008c22);
PHY_SetBBReg(pAdapter, rRx_IQK_Tone_B, bMaskDWord, 0x10008c22);
PHY_SetBBReg(pAdapter, rTx_IQK_PI_B, bMaskDWord, 0x82140102);
if(IS_HARDWARE_TYPE_8192D(pAdapter))
PHY_SetBBReg(pAdapter, rRx_IQK_PI_B, bMaskDWord, 0x28160206);
else
PHY_SetBBReg(pAdapter, rRx_IQK_PI_B, bMaskDWord, 0x28160202);
}
//LO calibration setting
RTPRINT(FINIT, INIT_IQK, ("LO calibration setting!\n"));
if(IS_HARDWARE_TYPE_8192D(pAdapter))
PHY_SetBBReg(pAdapter, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);
else
PHY_SetBBReg(pAdapter, rIQK_AGC_Rsp, bMaskDWord, 0x001028d1);
//One shot, path A LOK & IQK
RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n"));
PHY_SetBBReg(pAdapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
PHY_SetBBReg(pAdapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
// delay x ms
RTPRINT(FINIT, INIT_IQK, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME));
PlatformStallExecution(IQK_DELAY_TIME*1000);
// Check failed
regEAC = PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord);
RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", regEAC));
regE94 = PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord);
RTPRINT(FINIT, INIT_IQK, ("0xe94 = 0x%x\n", regE94));
regE9C= PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord);
RTPRINT(FINIT, INIT_IQK, ("0xe9c = 0x%x\n", regE9C));
regEA4= PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_A_2, bMaskDWord);
RTPRINT(FINIT, INIT_IQK, ("0xea4 = 0x%x\n", regEA4));
if(!(regEAC & BIT28) &&
(((regE94 & 0x03FF0000)>>16) != 0x142) &&
(((regE9C & 0x03FF0000)>>16) != 0x42) )
result |= 0x01;
else //if Tx not OK, ignore Rx
return result;
void getTxPowerWriteValByRegulatory(
struct net_device* dev,
u8 Channel,
u8 index,
u32* powerBase0,
u32* powerBase1,
u32* pOutWriteVal
)
{
struct r8192_priv *priv = rtllib_priv(dev);
u8 i, chnlGroup = 0, pwr_diff_limit[4];
u32 writeVal, customer_limit, rf;
for(rf=0; rf<2; rf++)
{
switch(priv->EEPROMRegulatory)
{
case 0:
chnlGroup = 0;
RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
chnlGroup, index, priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
writeVal = priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
((index<2)?powerBase0[rf]:powerBase1[rf]);
RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
break;
case 1:
if(priv->pwrGroupCnt == 1)
chnlGroup = 0;
if(priv->pwrGroupCnt >= 3)
{
if(Channel <= 3)
chnlGroup = 0;
else if(Channel >= 4 && Channel <= 9)
chnlGroup = 1;
else if(Channel > 9)
chnlGroup = 2;
if(priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
chnlGroup++;
else
chnlGroup+=4;
}
RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
chnlGroup, index, priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
writeVal = priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
((index<2)?powerBase0[rf]:powerBase1[rf]);
RTPRINT(FPHY, PHY_TXPWR, ("Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
break;
case 2:
writeVal = ((index<2)?powerBase0[rf]:powerBase1[rf]);
RTPRINT(FPHY, PHY_TXPWR, ("Better regulatory, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
break;
case 3:
chnlGroup = 0;
RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
chnlGroup, index, priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
{
RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 40MHz rf(%c) = 0x%x\n",
((rf==0)?'A':'B'), priv->PwrGroupHT40[rf][Channel-1]));
}
else
{
RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 20MHz rf(%c) = 0x%x\n",
((rf==0)?'A':'B'), priv->PwrGroupHT20[rf][Channel-1]));
}
for (i=0; i<4; i++)
{
pwr_diff_limit[i] = (u8)((priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]&(0x7f<<(i*8)))>>(i*8));
if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
{
if(pwr_diff_limit[i] > priv->PwrGroupHT40[rf][Channel-1])
pwr_diff_limit[i] = priv->PwrGroupHT40[rf][Channel-1];
}
else
{
if(pwr_diff_limit[i] > priv->PwrGroupHT20[rf][Channel-1])
pwr_diff_limit[i] = priv->PwrGroupHT20[rf][Channel-1];
}
}
customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) |
(pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]);
RTPRINT(FPHY, PHY_TXPWR, ("Customer's limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_limit));
writeVal = customer_limit + ((index<2)?powerBase0[rf]:powerBase1[rf]);
RTPRINT(FPHY, PHY_TXPWR, ("Customer, writeVal rf(%c)= 0x%x\n", ((rf==0)?'A':'B'), writeVal));
break;
default:
chnlGroup = 0;
writeVal = priv->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
((index<2)?powerBase0[rf]:powerBase1[rf]);
RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
break;
}
#ifdef ENABLE_DYNAMIC_TXPOWER
{
if(priv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
writeVal = 0x14141414;
else if(priv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
writeVal = 0x00000000;
}
#else
{
if(priv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)
{
RTPRINT(FBT, BT_TRACE, ("Tx Power (-6)\n"));
writeVal = writeVal - 0x06060606;
}
else if(priv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2)
{
RTPRINT(FBT, BT_TRACE, ("Tx Power (-0)\n"));
writeVal = writeVal ;
}
}
/*
else
{
if(priv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)
writeVal = writeVal - 0x06060606;
else if(priv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2)
writeVal = writeVal - 0x0c0c0c0c;
}
*/
#endif
*(pOutWriteVal+rf) = writeVal;
}
}
extern void
PHY_RF6052SetCckTxPower(
struct net_device* dev,
u8* pPowerlevel)
{
struct r8192_priv *priv = rtllib_priv(dev);
u32 TxAGC[2]={0, 0}, tmpval=0;
bool TurboScanOff=false;
u8 idx1, idx2;
u8* ptr;
if (priv->EEPROMRegulatory != 0)
TurboScanOff = true;
if(rtllib_act_scanning(priv->rtllib,true) == true)
{
TxAGC[RF90_PATH_A] = 0x3f3f3f3f;
TxAGC[RF90_PATH_B] = 0x3f3f3f3f;
if(TurboScanOff)
{
for(idx1=RF90_PATH_A; idx1<=RF90_PATH_B; idx1++)
{
TxAGC[idx1] =
pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
}
}
}
else
{
#ifdef ENABLE_DYNAMIC_TXPOWER
if(priv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
{
TxAGC[RF90_PATH_A] = 0x10101010;
TxAGC[RF90_PATH_B] = 0x10101010;
}
else if(priv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
{
TxAGC[RF90_PATH_A] = 0x00000000;
TxAGC[RF90_PATH_B] = 0x00000000;
}
else
#endif
{
for(idx1=RF90_PATH_A; idx1<=RF90_PATH_B; idx1++)
{
TxAGC[idx1] =
pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
}
if(priv->EEPROMRegulatory==0)
{
tmpval = (priv->MCSTxPowerLevelOriginalOffset[0][6]) +
(priv->MCSTxPowerLevelOriginalOffset[0][7]<<8);
TxAGC[RF90_PATH_A] += tmpval;
tmpval = (priv->MCSTxPowerLevelOriginalOffset[0][14]) +
(priv->MCSTxPowerLevelOriginalOffset[0][15]<<24);
TxAGC[RF90_PATH_B] += tmpval;
}
}
}
for(idx1=RF90_PATH_A; idx1<=RF90_PATH_B; idx1++)
{
ptr = (u8*)(&(TxAGC[idx1]));
for(idx2=0; idx2<4; idx2++)
{
if(*ptr > RF6052_MAX_TX_PWR)
*ptr = RF6052_MAX_TX_PWR;
ptr++;
}
}
tmpval = TxAGC[RF90_PATH_A]&0xff;
PHY_SetBBReg(dev, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval);
RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_A_CCK1_Mcs32));
tmpval = TxAGC[RF90_PATH_A]>>8;
if(priv->rtllib->mode == WIRELESS_MODE_B)
tmpval = tmpval & 0xff00ffff;
PHY_SetBBReg(dev, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11));
tmpval = TxAGC[RF90_PATH_B]>>24;
PHY_SetBBReg(dev, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval);
RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11));
tmpval = TxAGC[RF90_PATH_B]&0x00ffffff;
PHY_SetBBReg(dev, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n",
tmpval, rTxAGC_B_CCK1_55_Mcs32));
} /* PHY_RF6052SetCckTxPower */
void rtl8723be_phy_rf6052_set_cck_txpower( struct ieee80211_hw *hw,
u8 *ppowerlevel )
{
struct rtl_priv *rtlpriv = rtl_priv( hw );
struct rtl_phy *rtlphy = &( rtlpriv->phy );
struct rtl_mac *mac = rtl_mac( rtl_priv( hw ) );
struct rtl_efuse *rtlefuse = rtl_efuse( rtl_priv( hw ) );
u32 tx_agc[2] = {0, 0}, tmpval;
bool turbo_scanoff = false;
u8 idx1, idx2;
u8 *ptr;
u8 direction;
u32 pwrtrac_value;
if ( rtlefuse->eeprom_regulatory != 0 )
turbo_scanoff = true;
if ( mac->act_scanning ) {
tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
if ( turbo_scanoff ) {
for ( idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++ ) {
tx_agc[idx1] = ppowerlevel[idx1] |
( ppowerlevel[idx1] << 8 ) |
( ppowerlevel[idx1] << 16 ) |
( ppowerlevel[idx1] << 24 );
}
}
} else {
for ( idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++ ) {
tx_agc[idx1] = ppowerlevel[idx1] |
( ppowerlevel[idx1] << 8 ) |
( ppowerlevel[idx1] << 16 ) |
( ppowerlevel[idx1] << 24 );
}
if ( rtlefuse->eeprom_regulatory == 0 ) {
tmpval =
( rtlphy->mcs_txpwrlevel_origoffset[0][6] ) +
( rtlphy->mcs_txpwrlevel_origoffset[0][7] << 8 );
tx_agc[RF90_PATH_A] += tmpval;
tmpval = ( rtlphy->mcs_txpwrlevel_origoffset[0][14] ) +
( rtlphy->mcs_txpwrlevel_origoffset[0][15] <<
24 );
tx_agc[RF90_PATH_B] += tmpval;
}
}
for ( idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++ ) {
ptr = ( u8 * )( &( tx_agc[idx1] ) );
for ( idx2 = 0; idx2 < 4; idx2++ ) {
if ( *ptr > RF6052_MAX_TX_PWR )
*ptr = RF6052_MAX_TX_PWR;
ptr++;
}
}
rtl8723be_dm_txpower_track_adjust( hw, 1, &direction, &pwrtrac_value );
if ( direction == 1 ) {
tx_agc[0] += pwrtrac_value;
tx_agc[1] += pwrtrac_value;
} else if ( direction == 2 ) {
tx_agc[0] -= pwrtrac_value;
tx_agc[1] -= pwrtrac_value;
}
tmpval = tx_agc[RF90_PATH_A] & 0xff;
rtl_set_bbreg( hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval );
RTPRINT( rtlpriv, FPHY, PHY_TXPWR,
"CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
RTXAGC_A_CCK1_MCS32 );
tmpval = tx_agc[RF90_PATH_A] >> 8;
/*tmpval = tmpval & 0xff00ffff;*/
rtl_set_bbreg( hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval );
RTPRINT( rtlpriv, FPHY, PHY_TXPWR,
"CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
RTXAGC_B_CCK11_A_CCK2_11 );
tmpval = tx_agc[RF90_PATH_B] >> 24;
rtl_set_bbreg( hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval );
RTPRINT( rtlpriv, FPHY, PHY_TXPWR,
"CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
RTXAGC_B_CCK11_A_CCK2_11 );
tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff;
rtl_set_bbreg( hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval );
RTPRINT( rtlpriv, FPHY, PHY_TXPWR,
"CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
RTXAGC_B_CCK1_55_MCS32 );
}
static void _rtl8723be_get_txpower_writeval_by_regulatory(
struct ieee80211_hw *hw,
u8 channel, u8 index,
u32 *powerbase0,
u32 *powerbase1,
u32 *p_outwriteval )
{
struct rtl_priv *rtlpriv = rtl_priv( hw );
struct rtl_phy *rtlphy = &( rtlpriv->phy );
struct rtl_efuse *rtlefuse = rtl_efuse( rtl_priv( hw ) );
u8 i, chnlgroup = 0, pwr_diff_limit[4], pwr_diff = 0, customer_pwr_diff;
u32 writeval, customer_limit, rf;
for ( rf = 0; rf < 2; rf++ ) {
switch ( rtlefuse->eeprom_regulatory ) {
case 0:
chnlgroup = 0;
writeval =
rtlphy->mcs_txpwrlevel_origoffset[chnlgroup][index +
( rf ? 8 : 0 )]
+ ( ( index < 2 ) ? powerbase0[rf] : powerbase1[rf] );
RTPRINT( rtlpriv, FPHY, PHY_TXPWR,
"RTK better performance, writeval(%c) = 0x%x\n",
( ( rf == 0 ) ? 'A' : 'B' ), writeval );
break;
case 1:
if ( rtlphy->pwrgroup_cnt == 1 ) {
chnlgroup = 0;
} else {
if ( channel < 3 )
chnlgroup = 0;
else if ( channel < 6 )
chnlgroup = 1;
else if ( channel < 9 )
chnlgroup = 2;
else if ( channel < 12 )
chnlgroup = 3;
else if ( channel < 14 )
chnlgroup = 4;
else if ( channel == 14 )
chnlgroup = 5;
}
writeval =
rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
[index + ( rf ? 8 : 0 )] + ( ( index < 2 ) ?
powerbase0[rf] :
powerbase1[rf] );
RTPRINT( rtlpriv, FPHY, PHY_TXPWR,
"Realtek regulatory, 20MHz, writeval(%c) = 0x%x\n",
( ( rf == 0 ) ? 'A' : 'B' ), writeval );
break;
case 2:
writeval =
( ( index < 2 ) ? powerbase0[rf] : powerbase1[rf] );
RTPRINT( rtlpriv, FPHY, PHY_TXPWR,
"Better regulatory, writeval(%c) = 0x%x\n",
( ( rf == 0 ) ? 'A' : 'B' ), writeval );
break;
case 3:
chnlgroup = 0;
if ( rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40 ) {
RTPRINT( rtlpriv, FPHY, PHY_TXPWR,
"customer's limit, 40MHz rf(%c) = 0x%x\n",
( ( rf == 0 ) ? 'A' : 'B' ),
rtlefuse->pwrgroup_ht40
[rf][channel - 1] );
} else {
RTPRINT( rtlpriv, FPHY, PHY_TXPWR,
"customer's limit, 20MHz rf(%c) = 0x%x\n",
( ( rf == 0 ) ? 'A' : 'B' ),
rtlefuse->pwrgroup_ht20
[rf][channel - 1] );
}
if ( index < 2 )
pwr_diff =
rtlefuse->txpwr_legacyhtdiff[rf][channel-1];
else if ( rtlphy->current_chan_bw ==
HT_CHANNEL_WIDTH_20 )
pwr_diff =
rtlefuse->txpwr_ht20diff[rf][channel-1];
if ( rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40 )
customer_pwr_diff =
rtlefuse->pwrgroup_ht40[rf][channel-1];
else
customer_pwr_diff =
rtlefuse->pwrgroup_ht20[rf][channel-1];
if ( pwr_diff > customer_pwr_diff )
pwr_diff = 0;
else
pwr_diff = customer_pwr_diff - pwr_diff;
for ( i = 0; i < 4; i++ ) {
pwr_diff_limit[i] =
( u8 )( ( rtlphy->mcs_txpwrlevel_origoffset
[chnlgroup][index + ( rf ? 8 : 0 )] &
( 0x7f << ( i * 8 ) ) ) >> ( i * 8 ) );
if ( pwr_diff_limit[i] > pwr_diff )
pwr_diff_limit[i] = pwr_diff;
}
customer_limit = ( pwr_diff_limit[3] << 24 ) |
( pwr_diff_limit[2] << 16 ) |
( pwr_diff_limit[1] << 8 ) |
( pwr_diff_limit[0] );
RTPRINT( rtlpriv, FPHY, PHY_TXPWR,
"Customer's limit rf(%c) = 0x%x\n",
( ( rf == 0 ) ? 'A' : 'B' ), customer_limit );
writeval = customer_limit + ( ( index < 2 ) ?
powerbase0[rf] :
powerbase1[rf] );
RTPRINT( rtlpriv, FPHY, PHY_TXPWR,
"Customer, writeval rf(%c)= 0x%x\n",
( ( rf == 0 ) ? 'A' : 'B' ), writeval );
break;
default:
chnlgroup = 0;
writeval =
rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
[index + ( rf ? 8 : 0 )]
+ ( ( index < 2 ) ? powerbase0[rf] : powerbase1[rf] );
RTPRINT( rtlpriv, FPHY, PHY_TXPWR,
"RTK better performance, writeval rf(%c) = 0x%x\n",
( ( rf == 0 ) ? 'A' : 'B' ), writeval );
break;
}
if ( rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1 )
writeval = writeval - 0x06060606;
else if ( rtlpriv->dm.dynamic_txhighpower_lvl ==
TXHIGHPWRLEVEL_BT2 )
writeval = writeval - 0x0c0c0c0c;
*( p_outwriteval + rf ) = writeval;
}
}
static bool rtl8192_radio_on_off_checking(struct net_device *dev)
{
struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
u8 u1Tmp = 0;
u8 gpio;
if (priv->pwrdown) {
u1Tmp = read_nic_byte(dev, 0x06);
gpio = u1Tmp & BIT6;
} else
#ifdef CONFIG_BT_COEXIST
if (pHalData->bt_coexist.BluetoothCoexist) {
if (pHalData->bt_coexist.BT_CoexistType == BT_2Wire) {
PlatformEFIOWrite1Byte(pAdapter, MAC_PINMUX_CFG, 0xa);
u1Tmp = PlatformEFIORead1Byte(pAdapter, GPIO_IO_SEL);
delay_us(100);
u1Tmp = PlatformEFIORead1Byte(pAdapter, GPIO_IN);
RTPRINT(FPWR, PWRHW, ("GPIO_IN=%02x\n", u1Tmp));
retval = (u1Tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? eRfOn : eRfOff;
} else if ((pHalData->bt_coexist.BT_CoexistType == BT_ISSC_3Wire) ||
(pHalData->bt_coexist.BT_CoexistType == BT_Accel) ||
(pHalData->bt_coexist.BT_CoexistType == BT_CSR_BC4)) {
u4tmp = PHY_QueryBBReg(pAdapter, 0x87c, bMaskDWord);
if ((u4tmp & BIT17) != 0) {
PHY_SetBBReg(pAdapter, 0x87c, bMaskDWord, u4tmp & ~BIT17);
delay_us(50);
RTPRINT(FBT, BT_RFPoll, ("BT write 0x87c (~BIT17) = 0x%x\n", u4tmp &~BIT17));
}
u4tmp = PHY_QueryBBReg(pAdapter, 0x8e0, bMaskDWord);
RTPRINT(FBT, BT_RFPoll, ("BT read 0x8e0 (BIT24)= 0x%x\n", u4tmp));
retval = (u4tmp & BIT24) ? eRfOn : eRfOff;
RTPRINT(FBT, BT_RFPoll, ("BT check RF state to %s\n", (retval==eRfOn)? "ON":"OFF"));
}
} else
#endif
{
write_nic_byte(dev, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
u1Tmp = read_nic_byte(dev, GPIO_IO_SEL);
u1Tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
write_nic_byte(dev, GPIO_IO_SEL, u1Tmp);
mdelay(10);
u1Tmp = read_nic_byte(dev, GPIO_IN);
gpio = u1Tmp & HAL_8192S_HW_GPIO_OFF_BIT;
}
#ifdef DEBUG_RFKILL
{
static u8 gpio_test;
printk("%s: gpio = %x\n", __FUNCTION__, gpio);
if(gpio_test % 5 == 0) {
gpio = 0;
} else {
gpio = 1;
}
printk("%s: gpio_test = %d, gpio = %x\n", __FUNCTION__, gpio_test++ % 20, gpio);
}
#endif
return gpio;
}
void rtl92su_read_eeprom_info(struct ieee80211_hw *hw)
{
struct rtl_priv *rtlpriv = rtl_priv(hw);
struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
struct rtl_phy *rtlphy = &(rtlpriv->phy);
struct r92su_eeprom eeprom;
u16 i, eeprom_id;
u8 tempval;
u8 rf_path, index;
rtl92s_read_eeprom_info(hw);
switch (rtlefuse->epromtype) {
case EEPROM_BOOT_EFUSE:
rtl_efuse_shadow_map_update(hw);
break;
case EEPROM_93C46:
pr_err("RTL819X Not boot from eeprom, check it !!\n");
return;
default:
pr_warn("rtl92su: no efuse data\n\n");
return;
}
memcpy(&eeprom, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
HWSET_MAX_SIZE_92S);
RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP",
&eeprom, sizeof(eeprom));
eeprom_id = le16_to_cpu(eeprom.id);
if (eeprom_id != RTL8190_EEPROM_ID) {
RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
"EEPROM ID(%#x) is invalid!!\n", eeprom_id);
rtlefuse->autoload_failflag = true;
return;
}
RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
rtlefuse->autoload_failflag = false;
rtl92s_get_IC_Inferiority(hw);
/* Read IC Version && Channel Plan */
/* VID, DID SE 0xA-D */
rtlefuse->eeprom_vid = le16_to_cpu(eeprom.vid);
rtlefuse->eeprom_did = le16_to_cpu(eeprom.did);
rtlefuse->eeprom_svid = 0;
rtlefuse->eeprom_smid = 0;
rtlefuse->eeprom_version = eeprom.version;
RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
"EEPROMId = 0x%4x\n", eeprom_id);
RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
"EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
"EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
"EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
"EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
ether_addr_copy(rtlefuse->dev_addr, eeprom.mac_addr);
for (i = 0; i < 6; i++)
rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
/* Get Tx Power Level by Channel */
/* Read Tx power of Channel 1 ~ 14 from EEPROM. */
/* 92S suupport RF A & B */
for (rf_path = 0; rf_path < RF_PATH; rf_path++) {
for (i = 0; i < CHAN_SET; i++) {
/* Read CCK RF A & B Tx power */
rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
eeprom.tx_pwr_cck[rf_path][i];
/* Read OFDM RF A & B Tx power for 1T */
rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
eeprom.tx_pwr_ht40_1t[rf_path][i];
/* Read OFDM RF A & B Tx power for 2T */
rtlefuse->eprom_chnl_txpwr_ht40_2sdf[rf_path][i] =
eeprom.tx_pwr_ht40_2t[rf_path][i];
}
}
for (rf_path = 0; rf_path < RF_PATH; rf_path++) {
for (i = 0; i < CHAN_SET; i++) {
/* Read Power diff limit. */
rtlefuse->eeprom_pwrgroup[rf_path][i] =
eeprom.tx_pwr_edge[rf_path][i];
}
}
for (rf_path = 0; rf_path < RF_PATH; rf_path++)
for (i = 0; i < CHAN_SET; i++)
RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
"RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
rf_path, i,
rtlefuse->eeprom_chnlarea_txpwr_cck
[rf_path][i]);
for (rf_path = 0; rf_path < RF_PATH; rf_path++)
for (i = 0; i < CHAN_SET; i++)
RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
"RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
rf_path, i,
rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
[rf_path][i]);
for (rf_path = 0; rf_path < RF_PATH; rf_path++)
for (i = 0; i < CHAN_SET; i++)
RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
"RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
rf_path, i,
rtlefuse->eprom_chnl_txpwr_ht40_2sdf
[rf_path][i]);
for (rf_path = 0; rf_path < RF_PATH; rf_path++) {
/* Assign dedicated channel tx power */
for (i = 0; i < 14; i++) {
/* channel 1~3 use the same Tx Power Level. */
if (i < 3)
index = 0;
/* Channel 4-8 */
else if (i < 8)
index = 1;
/* Channel 9-14 */
else
index = 2;
/* Record A & B CCK /OFDM - 1T/2T Channel area
* tx power */
rtlefuse->txpwrlevel_cck[rf_path][i] =
rtlefuse->eeprom_chnlarea_txpwr_cck
[rf_path][index];
rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
[rf_path][index];
rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
rtlefuse->eprom_chnl_txpwr_ht40_2sdf
[rf_path][index];
}
for (i = 0; i < 14; i++) {
RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
"RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
rf_path, i,
rtlefuse->txpwrlevel_cck[rf_path][i],
rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
}
}
for (rf_path = 0; rf_path < 2; rf_path++) {
/* Fill Pwr group */
for (i = 0; i < 14; i++) {
/* Chanel 1-3 */
if (i < 3)
index = 0;
/* Channel 4-8 */
else if (i < 8)
index = 1;
/* Channel 9-13 */
else
index = 2;
rtlefuse->pwrgroup_ht20[rf_path][i] =
(rtlefuse->eeprom_pwrgroup[rf_path][index] &
0xf);
rtlefuse->pwrgroup_ht40[rf_path][i] =
((rtlefuse->eeprom_pwrgroup[rf_path][index] &
0xf0) >> 4);
RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
"RF-%d pwrgroup_ht20[%d] = 0x%x\n",
rf_path, i,
rtlefuse->pwrgroup_ht20[rf_path][i]);
RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
"RF-%d pwrgroup_ht40[%d] = 0x%x\n",
rf_path, i,
rtlefuse->pwrgroup_ht40[rf_path][i]);
}
}
for (i = 0; i < 14; i++) {
/* Read tx power difference between HT OFDM 20/40 MHZ */
/* channel 1-3 */
if (i < 3)
index = 0;
/* Channel 4-8 */
else if (i < 8)
index = 1;
/* Channel 9-14 */
else
index = 2;
tempval = eeprom.tx_pwr_ht20_diff[index] & 0xff;
rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
((tempval >> 4) & 0xF);
/* Read OFDM<->HT tx power diff */
/* Channel 1-3 */
if (i < 3)
tempval = eeprom.tx_pwr_ofdm_diff[0];
/* Channel 4-8 */
else if (i < 8)
tempval = eeprom.tx_pwr_ofdm_diff_cont;
/* Channel 9-14 */
else
tempval = eeprom.tx_pwr_ofdm_diff[1];
rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] =
(tempval & 0xF);
rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
((tempval >> 4) & 0xF);
tempval = eeprom.tx_pwr_edge_chk;
rtlefuse->txpwr_safetyflag = (tempval & 0x01);
}
rtlefuse->eeprom_regulatory = 0;
if (rtlefuse->eeprom_version >= 2) {
/* BIT(0)~2 */
if (rtlefuse->eeprom_version >= 4)
rtlefuse->eeprom_regulatory =
(eeprom.regulatory & 0x7);
else /* BIT(0) */
rtlefuse->eeprom_regulatory =
(eeprom.regulatory & 0x1);
}
RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
"eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
for (i = 0; i < 14; i++)
RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
"RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
for (i = 0; i < 14; i++)
RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
"RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
for (i = 0; i < 14; i++)
RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
"RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
for (i = 0; i < 14; i++)
RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
"RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
"TxPwrSafetyFlag = %d\n", rtlefuse->txpwr_safetyflag);
/* Read RF-indication and Tx Power gain
* index diff of legacy to HT OFDM rate. */
tempval = eeprom.rf_ind_power_diff & 0xff;
rtlefuse->eeprom_txpowerdiff = tempval;
rtlefuse->legacy_httxpowerdiff =
rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][0];
RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
"TxPowerDiff = %#x\n", rtlefuse->eeprom_txpowerdiff);
/* Get TSSI value for each path. */
rtlefuse->eeprom_tssi[RF90_PATH_A] = eeprom.tssi[RF90_PATH_A];
rtlefuse->eeprom_tssi[RF90_PATH_B] = eeprom.tssi[RF90_PATH_B];
RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
rtlefuse->eeprom_tssi[RF90_PATH_A],
rtlefuse->eeprom_tssi[RF90_PATH_B]);
/* Read antenna tx power offset of B/C/D to A from EEPROM */
/* and read ThermalMeter from EEPROM */
tempval = eeprom.thermal_meter;
rtlefuse->eeprom_thermalmeter = tempval;
RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
"thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
/* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */
rtlefuse->thermalmeter[0] = (rtlefuse->eeprom_thermalmeter & 0x1f);
rtlefuse->tssi_13dbm = rtlefuse->eeprom_thermalmeter * 100;
/* Read CrystalCap from EEPROM */
rtlefuse->eeprom_crystalcap = eeprom.crystal_cap >> 4;
/* CrystalCap, BIT(12)~15 */
rtlefuse->crystalcap = rtlefuse->eeprom_crystalcap;
/* Read IC Version && Channel Plan */
/* Version ID, Channel plan */
rtlefuse->eeprom_channelplan = eeprom.channel_plan;
rtlefuse->txpwr_fromeprom = true;
RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
"EEPROM ChannelPlan = 0x%4x\n", rtlefuse->eeprom_channelplan);
/* Read Customer ID or Board Type!!! */
tempval = eeprom.board_type;
/* Change RF type definition */
if (tempval == 0)
rtlphy->rf_type = RF_1T1R;
else if (tempval == 1)
rtlphy->rf_type = RF_1T2R;
else if (tempval == 2)
rtlphy->rf_type = RF_2T2R;
else if (tempval == 3)
rtlphy->rf_type = RF_1T1R;
/* 1T2R but 1SS (1x1 receive combining) */
rtlefuse->b1x1_recvcombine = false;
if (rtlphy->rf_type == RF_1T2R) {
tempval = rtl_read_byte(rtlpriv, 0x07);
if (!(tempval & BIT(0))) {
rtlefuse->b1x1_recvcombine = true;
RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
"RF_TYPE=1T2R but only 1SS\n");
}
}
rtlefuse->b1ss_support = rtlefuse->b1x1_recvcombine;
rtlefuse->eeprom_oemid = eeprom.custom_id;
RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x\n",
rtlefuse->eeprom_oemid);
/* set channel plan to world wide 13 */
rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
}
static VOID
ReadTxPowerInfo(
IN PADAPTER Adapter,
IN u8* PROMContent,
IN BOOLEAN AutoLoadFail
)
{
EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
TxPowerInfo pwrInfo;
u32 rfPath, ch, group;
u8 pwr, diff;
_ReadPowerValueFromPROM(&pwrInfo, PROMContent, AutoLoadFail);
for(rfPath = 0 ; rfPath < RF90_PATH_MAX ; rfPath++){
for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
group = _GetChannelGroup(ch);
pEEPROM->TxPwrLevelCck[rfPath][ch] = pwrInfo.CCKIndex[rfPath][group];
pEEPROM->TxPwrLevelHT40_1S[rfPath][ch] = pwrInfo.HT40_1SIndex[rfPath][group];
pEEPROM->TxPwrHt20Diff[rfPath][ch] = pwrInfo.HT20IndexDiff[rfPath][group];
pEEPROM->TxPwrLegacyHtDiff[rfPath][ch] = pwrInfo.OFDMIndexDiff[rfPath][group];
pEEPROM->PwrGroupHT20[rfPath][ch] = pwrInfo.HT20MaxOffset[rfPath][group];
pEEPROM->PwrGroupHT40[rfPath][ch] = pwrInfo.HT40MaxOffset[rfPath][group];
pwr = pwrInfo.HT40_1SIndex[rfPath][group];
diff = pwrInfo.HT40_2SIndexDiff[rfPath][group];
pEEPROM->TxPwrLevelHT40_2S[rfPath][ch] = (pwr > diff) ? (pwr - diff) : 0;
}
}
if(AutoLoadFail)
{
pEEPROM->EEPROMRegulatory= 0;
}
else
{
pEEPROM->EEPROMRegulatory = (PROMContent[EEPROM_RF_OPT1]&0x7); //bit0~2
}
#if DBG
for(rfPath = 0 ; rfPath < RF90_PATH_MAX ; rfPath++){
for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
RTPRINT(FINIT, INIT_TxPower,
("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
rfPath, ch, pHalData->TxPwrLevelCck[rfPath][ch],
pHalData->TxPwrLevelHT40_1S[rfPath][ch],
pHalData->TxPwrLevelHT40_2S[rfPath][ch]));
}
}
for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
RTPRINT(FINIT, INIT_TxPower, ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrHt20Diff[RF90_PATH_A][ch]));
}
for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
RTPRINT(FINIT, INIT_TxPower, ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrLegacyHtDiff[RF90_PATH_A][ch]));
}
for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
RTPRINT(FINIT, INIT_TxPower, ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrHt20Diff[RF90_PATH_B][ch]));
}
for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){
RTPRINT(FINIT, INIT_TxPower, ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrLegacyHtDiff[RF90_PATH_B][ch]));
}
#endif
}
static void _rtl8723e_write_ofdm_power_reg( struct ieee80211_hw *hw,
u8 index, u32 *pvalue )
{
struct rtl_priv *rtlpriv = rtl_priv( hw );
struct rtl_phy *rtlphy = &rtlpriv->phy;
u16 regoffset_a[6] = {
RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24,
RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
};
u16 regoffset_b[6] = {
RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24,
RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
};
u8 i, rf, pwr_val[4];
u32 writeval;
u16 regoffset;
for ( rf = 0; rf < 2; rf++ ) {
writeval = pvalue[rf];
for ( i = 0; i < 4; i++ ) {
pwr_val[i] = ( u8 )( ( writeval & ( 0x7f <<
( i * 8 ) ) ) >> ( i * 8 ) );
if ( pwr_val[i] > RF6052_MAX_TX_PWR )
pwr_val[i] = RF6052_MAX_TX_PWR;
}
writeval = ( pwr_val[3] << 24 ) | ( pwr_val[2] << 16 ) |
( pwr_val[1] << 8 ) | pwr_val[0];
if ( rf == 0 )
regoffset = regoffset_a[index];
else
regoffset = regoffset_b[index];
rtl_set_bbreg( hw, regoffset, MASKDWORD, writeval );
RTPRINT( rtlpriv, FPHY, PHY_TXPWR,
"Set 0x%x = %08x\n", regoffset, writeval );
if ( ( ( get_rf_type( rtlphy ) == RF_2T2R ) &&
( regoffset == RTXAGC_A_MCS15_MCS12 ||
regoffset == RTXAGC_B_MCS15_MCS12 ) ) ||
( ( get_rf_type( rtlphy ) != RF_2T2R ) &&
( regoffset == RTXAGC_A_MCS07_MCS04 ||
regoffset == RTXAGC_B_MCS07_MCS04 ) ) ) {
writeval = pwr_val[3];
if ( regoffset == RTXAGC_A_MCS15_MCS12 ||
regoffset == RTXAGC_A_MCS07_MCS04 )
regoffset = 0xc90;
if ( regoffset == RTXAGC_B_MCS15_MCS12 ||
regoffset == RTXAGC_B_MCS07_MCS04 )
regoffset = 0xc98;
for ( i = 0; i < 3; i++ ) {
writeval = ( writeval > 6 ) ? ( writeval - 6 ) : 0;
rtl_write_byte( rtlpriv, ( u32 ) ( regoffset + i ),
( u8 )writeval );
}
}
}
}
