void us_ticker_init(void) {
if (us_ticker_inited) return;
us_ticker_inited = 1;
/* set Counter Clock(us) */
if (false == RZ_A1_IsClockMode0()) {
count_clock = ((double)CM1_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV);
} else {
count_clock = ((double)CM0_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV);
}
/* Power Control for Peripherals */
CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP50); /* enable OSTM1 clock */
// timer settings
OSTM1TT = 0x01; /* Stop the counter and clears the OSTM1TE bit. */
OSTM1CTL = 0x02; /* Free running timer mode. Interrupt disabled when star counter */
OSTM1TS = 0x1; /* Start the counter and sets the OSTM0TE bit. */
// INTC settings
InterruptHandlerRegister(US_TICKER_TIMER_IRQn, (void (*)(uint32_t))us_ticker_interrupt);
GIC_SetPriority(US_TICKER_TIMER_IRQn, 5);
GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
}
void start1msecInterrupt(void (*func)(void))
{
static bool started = false;
if (!started) {
CPG.STBCR5 &= ~CpgStbcr5Bit; // OsTimer power supply
OsTimer.OSTMnTT = 0b00000001; // Timer stop
msecCount = 0;
InterruptHandlerRegister(WrapAroundIrq, (IRQHandler)func);
GIC_SetPriority(WrapAroundIrq, 5);
GIC_EnableIRQ(WrapAroundIrq);
if (RZ_A1_IsClockMode0()) {
phy0ClockPeriod = CM0_RENESAS_RZ_A1_P0_CLK / 1000;
} else {
phy0ClockPeriod = CM1_RENESAS_RZ_A1_P0_CLK / 1000;
}
OsTimer.OSTMnCMP = phy0ClockPeriod - 1; // Interrupt generation timing
OsTimer.OSTMnCTL = 0b00000000; // Interval timer mode
// Interrupts disabled at count start
OsTimer.OSTMnTS = 0b00000001; // Count start
started = true;
}
}
void i2c_frequency(i2c_t *obj, int hz) {
int freq;
int oldfreq = 0;
int newfreq = 0;
uint32_t pclk;
uint32_t pclk_base;
uint32_t tmp_width;
uint32_t width = 0;
uint8_t count;
uint8_t pclk_bit = 0;
/* set PCLK */
if (false == RZ_A1_IsClockMode0()) {
pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK;
} else {
pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK;
}
/* Min 10kHz, Max 400kHz */
if (hz < 10000) {
freq = 10000;
} else if (hz > 400000) {
freq = 400000;
} else {
freq = hz;
}
for (count = 0; count < 7; count++) {
// IIC phi = P0 phi / rate
pclk = pclk_base / (2 << count);
// In case of "CLE = 1, NFE = 1, CKS != 000( IIC phi < P0 phi ), nf = 1"
// freq = 1 / {[( BRH + 2 + 1 ) + ( BRL + 2 + 1 )] / pclk }
// BRH is regarded as same value with BRL
// 2( BRH + 3 ) / pclk = 1 / freq
tmp_width = ((pclk / freq) / 2) - 3;
// Carry in a decimal point
tmp_width += 1;
if ((tmp_width >= 0x00000001) && (tmp_width <= 0x0000001F)) {
// Calculate theoretical value, and Choose max value of them
newfreq = pclk / (tmp_width + 3) / 2;
if (newfreq >= oldfreq) {
oldfreq = newfreq;
width = tmp_width;
pclk_bit = (uint8_t)(0x10 * (count + 1));
}
}
}
if (width != 0) {
// I2C Rate
obj->pclk_bit = pclk_bit; // P_phi / xx
obj->width = (width | 0x000000E0);
} else {
// Default
obj->pclk_bit = 0x00; // P_phi / 1
obj->width = 0x000000FF;
}
}
// Set the PWM period, keeping the duty cycle the same.
void pwmout_period_us(pwmout_t* obj, int us) {
uint64_t wk_cycle_mtu2;
uint32_t pclk_base;
uint32_t wk_cycle;
uint32_t wk_cks = 0;
uint16_t wk_last_cycle;
int max_us = 0;
if (obj->pwm >= MTU2_PWM_OFFSET) {
/* PWM by MTU2 */
int tmp_pwm;
uint8_t tmp_tcr_up;
uint8_t tmp_tstr_sp;
uint8_t tmp_tstr_st;
max_us = MAX_PERIOD[obj->ch];
if (us > max_us) {
us = max_us;
} else if (us < 1) {
us = 1;
} else {
// Do Nothing
}
if (RZ_A1_IsClockMode0() == false) {
pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK;
} else {
pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK;
}
wk_cycle_mtu2 = (uint64_t)pclk_base * us;
while (wk_cycle_mtu2 >= 65535000000) {
if ((obj->ch == 1) && (wk_cks == 3)) {
wk_cks+=2;
} else if ((obj->ch == 2) && (wk_cks == 3)) {
wk_cycle_mtu2 >>= 2;
wk_cks+=3;
}
wk_cycle_mtu2 >>= 2;
wk_cks++;
}
static void can_set_frequency(can_t *obj, int f) {
__IO uint32_t *dmy_cfg;
int oldfreq = 0;
int newfreq = 0;
uint32_t clkc_val;
uint8_t tmp_tq;
uint8_t tq = 0;
uint8_t tmp_brp;
uint8_t brp = 0;
uint8_t tseg1 = 0;
uint8_t tseg2 = 0;
uint8_t sjw = 0;
/* set clkc */
if (RZ_A1_IsClockMode0() == false) {
clkc_val = CM1_RENESAS_RZ_A1_P1_CLK / 2;
} else {
clkc_val = CM0_RENESAS_RZ_A1_P1_CLK / 2;
}
/* calculate BRP bit and Choose max value of calculated frequency */
for (tmp_tq = 8; tmp_tq <= 25; tmp_tq++) {
/* f = fCAN / ((BRP+1) * Tq) */
/* BRP = (fCAN / (f * Tq)) - 1 */
tmp_brp = ((clkc_val / (f * tmp_tq)) - 1) + 1; // carry(decimal point is carry)
newfreq = clkc_val / ((tmp_brp + 1) * tmp_tq);
if (newfreq >= oldfreq) {
oldfreq = newfreq;
tq = tmp_tq;
brp = tmp_brp;
}
}
/* calculate TSEG1 bit and TSEG2 bit */
tseg1 = (tq - 1) * 0.666666667;
tseg2 = (tq - 1) - tseg1;
sjw = (tseg2 > 4)? 4 : tseg2;
/* set RSCAN0CmCFG register */
dmy_cfg = CFG_MATCH[obj->ch];
*dmy_cfg = ((sjw - 1) << 24) | ((tseg2 - 1) << 20) | ((tseg1 - 1) << 16) | brp;
}
void spi_frequency(spi_t *obj, int hz) {
uint32_t pclk_base;
uint32_t div;
uint32_t brdv = 0;
uint32_t hz_max;
uint32_t hz_min;
uint16_t mask = 0x000c;
uint16_t wk_spcmd0;
/* set PCLK */
if (RZ_A1_IsClockMode0() == false) {
pclk_base = CM1_RENESAS_RZ_A1_P1_CLK;
} else {
pclk_base = CM0_RENESAS_RZ_A1_P1_CLK;
}
hz_min = pclk_base / 2 / 256 / 8;
hz_max = pclk_base / 2;
if ((hz < hz_min) || (hz > hz_max)) {
error("Couldn't setup requested SPI frequency");
return;
}
div = (pclk_base / hz / 2);
while (div > 256) {
div >>= 1;
brdv++;
}
div -= 1;
brdv = (brdv << 2);
spi_disable(obj);
obj->spi->SPBR = div;
wk_spcmd0 = obj->spi->SPCMD0;
wk_spcmd0 &= ~mask;
wk_spcmd0 |= (mask & brdv);
obj->spi->SPCMD0 = wk_spcmd0;
spi_enable(obj);
}
// Set the PWM period, keeping the duty cycle the same.
void pwmout_period_us(pwmout_t* obj, int us) {
uint32_t pclk_base;
uint32_t wk_cycle;
uint16_t wk_last_cycle;
uint32_t wk_cks = 0;
if (us > 491) {
us = 491;
} else if (us < 1) {
us = 1;
} else {
// Do Nothing
}
if (RZ_A1_IsClockMode0() == false) {
pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK / 10000;
} else {
pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK / 10000;
}
wk_cycle = pclk_base * us;
while (wk_cycle >= 102350) {
wk_cycle >>= 1;
wk_cks++;
}
wk_cycle = (wk_cycle + 50) / 100;
if (obj->ch == 2) {
wk_last_cycle = PWMPWCYR_2 & 0x03ff;
PWMPWCR_2_BYTE_L = 0xc0 | wk_cks;
PWMPWCYR_2 = (uint16_t)wk_cycle;
// Set duty again
set_duty_again(&PWMPWBFR_2A, wk_last_cycle, wk_cycle);
set_duty_again(&PWMPWBFR_2C, wk_last_cycle, wk_cycle);
set_duty_again(&PWMPWBFR_2E, wk_last_cycle, wk_cycle);
set_duty_again(&PWMPWBFR_2G, wk_last_cycle, wk_cycle);
// Counter Start
PWMPWCR_2_BYTE_L |= 0x08;
// Save for future use
period_ch2 = us;
} else {
wk_last_cycle = PWMPWCYR_1 & 0x03ff;
PWMPWCR_1_BYTE_L = 0xc0 | wk_cks;
PWMPWCYR_1 = (uint16_t)wk_cycle;
// Set duty again
set_duty_again(&PWMPWBFR_1A, wk_last_cycle, wk_cycle);
set_duty_again(&PWMPWBFR_1C, wk_last_cycle, wk_cycle);
set_duty_again(&PWMPWBFR_1E, wk_last_cycle, wk_cycle);
set_duty_again(&PWMPWBFR_1G, wk_last_cycle, wk_cycle);
// Counter Start
PWMPWCR_1_BYTE_L |= 0x08;
// Save for future use
period_ch1 = us;
}
}
void i2c_frequency(i2c_t *obj, int hz) {
float64_t pclk_val;
float64_t wait_utime;
volatile float64_t bps;
volatile float64_t L_time; /* H Width period */
volatile float64_t H_time; /* L Width period */
uint32_t tmp_L_width;
uint32_t tmp_H_width;
uint32_t remainder;
uint32_t wk_cks = 0;
/* set PCLK */
if (false == RZ_A1_IsClockMode0()) {
pclk_val = (float64_t)CM1_RENESAS_RZ_A1_P0_CLK;
} else {
pclk_val = (float64_t)CM0_RENESAS_RZ_A1_P0_CLK;
}
/* Min 10kHz, Max 400kHz */
if (hz < 10000) {
bps = 10000;
} else if (hz > 400000) {
bps = 400000;
} else {
bps = (float64_t)hz;
}
/* Calculation L width time */
L_time = (1 / (2 * bps)); /* Harf period of frequency */
H_time = L_time;
/* Check I2C mode of Speed */
if (bps > 100000) {
/* Fast-mode */
L_time -= 102E-9; /* Falling time of SCL clock. */
H_time -= 138E-9; /* Rising time of SCL clock. */
/* Check L wideth */
if (L_time < 1.3E-6) {
/* Wnen L width less than 1.3us */
/* Subtract Rise up and down time for SCL from H/L width */
L_time = 1.3E-6;
H_time = (1 / bps) - L_time - 138E-9 - 102E-9;
}
}
tmp_L_width = (uint32_t)(L_time * pclk_val * 10);
tmp_L_width >>= 1;
wk_cks++;
while (tmp_L_width >= 341) {
tmp_L_width >>= 1;
wk_cks++;
}
remainder = tmp_L_width % 10;
tmp_L_width = ((tmp_L_width + 9) / 10) - 3; /* carry */
tmp_H_width = (uint32_t)(H_time * pclk_val * 10);
tmp_H_width >>= wk_cks;
if (remainder == 0) {
tmp_H_width = ((tmp_H_width + 9) / 10) - 3; /* carry */
} else {
remainder += tmp_H_width % 10;
tmp_H_width = (tmp_H_width / 10) - 3;
if (remainder > 10) {
tmp_H_width += 1; /* fine adjustment */
}
}
/* timeout of BBSY bit is minimum low width by frequency */
/* so timeout calculates "(low width) * 2" by frequency */
wait_utime = (L_time * 2) * 1000000;
/* 1 wait of BBSY bit is about 0.3us. if it's below 0.3us, wait count is set as 1. */
if (wait_utime <= 0.3) {
obj->bbsy_wait_cnt = 1;
} else {
obj->bbsy_wait_cnt = (int)(wait_utime / 0.3);
}
/* I2C Rate */
obj->pclk_bit = (uint8_t)(0x10 * wk_cks); /* P_phi / xx */
obj->width_low = (uint8_t)(tmp_L_width | 0x000000E0);
obj->width_hi = (uint8_t)(tmp_H_width | 0x000000E0);
/* full reset */
i2c_reg_reset(obj);
}
