//------------------------------------------------------------------------------
// Function Name: SiI_CEC_GetCommand
// Function Description: This function gets data from CEC Reception
//
// Accepts: pSiI_CEC
// Returns: none
// Globals: none
//------------------------------------------------------------------------------
uint8_t SiI_CEC_GetCommand( SiI_CEC_t * pSiI_CEC )
{
uint8_t error = FALSE;
uint8_t bCount;
bCount = pSiI_CEC->bCount & 0x0f; // extract uint8_t counter, ignore frame counter
if ( !(pSiI_CEC->bCount & BIT_MSG_ERROR) )
RegisterReadBlock(REG__CEC_RX_CMD_HEADER, &pSiI_CEC->bDestOrRXHeader , bCount + 2);
else
error = 1;
// Clear CLR_RX_FIFO_CUR;
// Clear current frame from Rx FIFO
RegisterModify(REG__CEC_RX_CONTROL, BIT_CLR_RX_FIFO_CUR, BIT_CLR_RX_FIFO_CUR );
// Check if more frame in Rx FIFO, if yes get uint8_t count of next frame.
pSiI_CEC->bRXNextCount = 0;
if( pSiI_CEC->bCount & 0xF0 )
{
pSiI_CEC->bRXNextCount = RegisterRead(REG__CEC_RX_COUNT);
}
return error;
}
static void print_mpegbuffer( void ){
uint8_t abData[16];
RegisterReadBlock( REG__MPEG_TYPE, abData, 16 );
print_tabl ( "Mpeg_buf", abData, 16, 8 );
}
static void InterruptHandler(void)
{
uint8_t abIntrStatus[8];
uint8_t bNewInfoFrm = 0;
uint8_t bNoInfoFrm = 0;
//read all interrupt registers
RegisterReadBlock(REG__INTR1, &abIntrStatus[0], 4);
RegisterReadBlock(REG__INTR5, &abIntrStatus[4], 2);
RegisterReadBlock(REG__INTR7, &abIntrStatus[6], 2);
#if 0
DEBUG_PRINT(("i: %02X %02X %02X %02X %02X %02X %02X %02X\n",
(int)abIntrStatus[0],(int)abIntrStatus[1],(int)abIntrStatus[2],(int)abIntrStatus[3],
(int)abIntrStatus[4],(int)abIntrStatus[5],(int)abIntrStatus[6],(int)abIntrStatus[7]));
#endif
//clear all pending interrupts
RegisterWriteBlock(REG__INTR1, &abIntrStatus[0], 4);
RegisterWriteBlock(REG__INTR5, &abIntrStatus[4], 2);
RegisterWriteBlock(REG__INTR7, &abIntrStatus[6], 2);
#if (CONF__ODCK_LIMITED==ENABLE)
if (abIntrStatus[6] & BIT__PCLK_STOP) //ODCK stopped
{
DEBUG_PRINT(("ODCK stopped\n"));
ProcessOdckStop();
}
#endif //#if (CONF__ODCK_LIMITED==ENABLED)
// process pending interrupts
if (abIntrStatus[1] & BIT__SCDT_CHG) //if SCDT change
ProcessScdtModeChange();
if (abIntrStatus[4] & BIT__AACDONE) //if soft mute done
{
TurnAudioMute(ON);
CurrentStatus.AudioState = STATE_AUDIO__REQUEST_AUDIO;
}
#if (CONF__VSYNC_OVERFLOW == ENABLE)
if (abIntrStatus[4] & BIT__HRCHG ) //if H res change
#else
if (abIntrStatus[4] & (BIT__HRCHG|BIT__VRCHG)) //if H/V res change
#endif
{
#if (PEBBLES_ES1_FF_WORKAROUND == ENABLE)
if (!ProcessVhResolutionChange())
#endif
ConfigureDeepColor();
}
if (abIntrStatus[5] & BIT__NEW_ACP_PKT)
AcpPacketHandler(ON);
if (abIntrStatus[6] & BIT__VIDEO_READY) //video ready for unmute
{
DEBUG_PRINT(("Video rdy\n"));
TurnVideoMute(OFF);
}
if (abIntrStatus[7] & BIT__NO_ACP_INF) // no ACP pkt
AcpPacketHandler(OFF);
#if (CONF__SUPPORT_3D == ENABLE)
/***** Processing info frame interrupts ***********************/
bNewInfoFrm = abIntrStatus[INTR3_NEW_INFOFR] & INTR3_NEW_INFOFR_SEL;
bNoInfoFrm = abIntrStatus[INTR8_NEW_GMT_NO_INFOFR] & INTR8_NO_INFOFR_SEL;
if( abIntrStatus[INTR4_NO_AVI] & INTR4_NO_AVI_SEL ){
bNoInfoFrm |= BIT__VIRT_NO_AVI_INF;
}
if ( abIntrStatus[INTR8_NEW_GMT_NO_INFOFR] & BIT__NEW_GDB_INF ){
bNewInfoFrm |= BIT__VIRT_NEW_GDB_INF;
}
if ( abIntrStatus[INTR5_NEW_ACP] & BIT__NEW_ACP_PKT ){
bNewInfoFrm |= BIT__VIRT_NEW_ACP_INF;
}
/* Check if any of info frame interrupts has occured */
if( bNewInfoFrm || bNoInfoFrm ){
InterInfoFrmProc ( bNewInfoFrm, bNoInfoFrm );
}
#endif //#if (CONF__SUPPORT_3D == ENABLE)
/***** End Processing info frame interrupts ***********************/
}
//------------------------------------------------------------------------------
// Function Name: SiI_CEC_IntProcessing
// Function Description: This function is called on interrupt events
// it makes interrut service
// Accepts: SiI_CEC_Int_t * pInt
// Returns: none
// Globals: none
//------------------------------------------------------------------------------
uint8_t CEC_IntProcessing ( SiI_CEC_Int_t * pInt )
{
uint8_t error = FALSE;
uint8_t cec_int_status_reg[2];
// Get Interrupts
pInt->bTXState = 0;
pInt->bCECErrors = 0;
pInt->bRXState = 0;
RegisterReadBlock(REG__CEC_INT_STATUS_0,cec_int_status_reg,2);
{
// Poll Interrupt
if( (cec_int_status_reg[0] & 0x7F) || cec_int_status_reg[1] )
{
DEBUG_PRINT(("\nA6A7Reg: %02X %02X", (int) cec_int_status_reg[0], (int) cec_int_status_reg[1]));
// Clear interrupts
if ( cec_int_status_reg[1] & BIT_FRAME_RETRANSM_OV )
{
DEBUG_PRINT(("\n!CEC_A7_TX_RETRY_EXCEEDED![%02X][%02X]",(int) cec_int_status_reg[0], (int) cec_int_status_reg[1]));
// flash TX otherwise after writing clear interrupt
// BIT_FRAME_RETRANSM_OV the TX command will be re-send
RegisterModify(REG__CEC_DEBUG_3,BIT_FLUSH_TX_FIFO, BIT_FLUSH_TX_FIFO);
}
//
// Clear set bits that are set
//
RegisterWriteBlock(REG__CEC_INT_STATUS_0,cec_int_status_reg,2);
DEBUG_PRINT(("\nA6A7Reg: %02X %02X", (int) cec_int_status_reg[0], (int) cec_int_status_reg[1]));
// RX Processing
if ( cec_int_status_reg[0] & BIT_RX_MSG_RECEIVED )
{
// Save number of frames in Rx Buffer
pInt->bRXState = RegisterRead(REG__CEC_RX_COUNT);
}
// RX Errors processing
if ( cec_int_status_reg[1] & BIT_SHORT_PULSE_DET )
{
pInt->bCECErrors |= eSiI_CEC_ShortPulse;
}
if ( cec_int_status_reg[1] & BIT_START_IRREGULAR )
{
pInt->bCECErrors |= eSiI_CEC_StartIrregular;
}
if ( cec_int_status_reg[1] & BIT_RX_FIFO_OVERRUN ) // fixed per Uematsu san
{
pInt->bCECErrors |= eSiI_CEC_RXOverFlow;
}
// TX Processing
if ( cec_int_status_reg[0] & BIT_TX_FIFO_EMPTY ) //0x04
{
pInt->bTXState = eSiI_TXWaitCmd;
}
if ( cec_int_status_reg[0] & BIT_TX_MESSAGE_SENT ) //0x20
{
pInt->bTXState = eSiI_TXSendAcked;
}
if ( cec_int_status_reg[1] & BIT_FRAME_RETRANSM_OV ) //0x02
{
pInt->bTXState = eSiI_TXFailedToSend;
}
}
}
return error;
}
