C++ (Cpp) S5PC1XX_GPH3_OUTPUT Examples

Programming Language: C++ (Cpp)

Method/Function: S5PC1XX_GPH3_OUTPUT

Examples at hotexamples.com: 4

C++ (Cpp) S5PC1XX_GPH3_OUTPUT - 4 examples found. These are the top rated real world C++ (Cpp) examples of S5PC1XX_GPH3_OUTPUT extracted from open source projects. You can rate examples to help us improve the quality of examples.

Example #1

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/*
 * External camera reset
 * Because the most of cameras take i2c bus signal, so that
 * you have to reset at the boot time for other i2c slave devices.
 * Do optimization for cameras on your platform.
*/
static void smdkc100_reset_camera(void)
{
    void __iomem *regs = ioremap(S5PC1XX_PA_FIMC0, SZ_4K);
    u32 cfg;

    /* based on s5k4ba at the channel A */
#if 0
    /* high reset */
    cfg = readl(regs + S3C_CIGCTRL);
    cfg |= S3C_CIGCTRL_CAMRST_A;
    writel(cfg, regs + S3C_CIGCTRL);
    udelay(200);

    cfg = readl(regs + S3C_CIGCTRL);
    cfg &= ~S3C_CIGCTRL_CAMRST_A;
    writel(cfg, regs + S3C_CIGCTRL);
    udelay(2000);
#else
    /* low reset */
    cfg = readl(regs + S3C_CIGCTRL);
    cfg &= ~S3C_CIGCTRL_CAMRST_A;
    writel(cfg, regs + S3C_CIGCTRL);
    udelay(200);

    cfg = readl(regs + S3C_CIGCTRL);
    cfg |= S3C_CIGCTRL_CAMRST_A;
    writel(cfg, regs + S3C_CIGCTRL);
    udelay(2000);
#endif

#if 0
    /* channel B reset: should be done by following after ch A reset */
    cfg = readl(S5PC1XX_GPH3CON);
    cfg &= ~S5PC1XX_GPH3_CONMASK(6);
    cfg |= S5PC1XX_GPH3_OUTPUT(6);
    writel(cfg, S5PC1XX_GPH3CON);

    cfg = readl(S5PC1XX_GPH3DAT);
    cfg &= ~(0x1 << 6);
    writel(cfg, S5PC1XX_GPH3DAT);
    udelay(200);

    cfg |= (0x1 << 6);
    writel(cfg, S5PC1XX_GPH3DAT);
    udelay(2000);
#endif

    iounmap(regs);
}

Example #2

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File: s3c_fimc4x_regs.c Project: IoveSunny/DreamBox

void s3c_fimc_reset_camera(void)
{
	void __iomem *regs = ioremap(S5PC1XX_PA_FIMC0, SZ_4K);
	u32 cfg;

	
#if (CONFIG_VIDEO_FIMC_CAM_RESET == 1)
	printk("[CAM]Reset camera1.\n");
	cfg = readl(regs + S3C_CIGCTRL);
	cfg |= S3C_CIGCTRL_CAMRST_A;
	writel(cfg, regs + S3C_CIGCTRL);
	udelay(200);

	cfg = readl(regs + S3C_CIGCTRL);
	cfg &= ~S3C_CIGCTRL_CAMRST_A;
	writel(cfg, regs + S3C_CIGCTRL);
	udelay(2000);
#else
	printk("[CAM]Reset camera2.\n");
	cfg = readl(regs + S3C_CIGCTRL);
	cfg &= ~S3C_CIGCTRL_CAMRST_A;
	writel(cfg, regs + S3C_CIGCTRL);
	udelay(200);

	cfg = readl(regs + S3C_CIGCTRL);
	cfg |= S3C_CIGCTRL_CAMRST_A;
	writel(cfg, regs + S3C_CIGCTRL);
	udelay(2000);
#endif

#if (CONFIG_VIDEO_FIMC_CAM_CH == 1)
	cfg = readl(S5PC1XX_GPH3CON);
	cfg &= ~S5PC1XX_GPH3_CONMASK(6);
	cfg |= S5PC1XX_GPH3_OUTPUT(6);
	writel(cfg, S5PC1XX_GPH3CON);

	cfg = readl(S5PC1XX_GPH3DAT);
	cfg &= ~(0x1 << 6);
	writel(cfg, S5PC1XX_GPH3DAT);
	udelay(200);

	cfg |= (0x1 << 6);
	writel(cfg, S5PC1XX_GPH3DAT);
	udelay(2000);
#endif

	iounmap(regs);
}

Example #3

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int fimc_hw_reset_camera(struct fimc_control *ctrl)
{
	u32 cfg;

	/* based on s5k4ba at the channel A */
#if 0
	/* high reset */
	cfg = readl(ctrl->regs + S3C_CIGCTRL);
	cfg |= S3C_CIGCTRL_CAMRST_A;
	writel(cfg, ctrl->regs + S3C_CIGCTRL);
	udelay(200);

	cfg = readl(ctrl->regs + S3C_CIGCTRL);
	cfg &= ~S3C_CIGCTRL_CAMRST_A;
	writel(cfg, ctrl->regs + S3C_CIGCTRL);
	udelay(2000);
#else
	/* low reset */
	cfg = readl(ctrl->regs + S3C_CIGCTRL);
	cfg &= ~S3C_CIGCTRL_CAMRST_A;
	writel(cfg, ctrl->regs + S3C_CIGCTRL);
	udelay(200);

	cfg = readl(ctrl->regs + S3C_CIGCTRL);
	cfg |= S3C_CIGCTRL_CAMRST_A;
	writel(cfg, ctrl->regs + S3C_CIGCTRL);
	udelay(2000);
#endif

#if 0
	/* channel B reset: should be done by following after ch A reset */
	cfg = readl(S5PC1XX_GPH3CON);
	cfg &= ~S5PC1XX_GPH3_CONMASK(6);
	cfg |= S5PC1XX_GPH3_OUTPUT(6);
	writel(cfg, S5PC1XX_GPH3CON);

	cfg = readl(S5PC1XX_GPH3DAT);
	cfg &= ~(0x1 << 6);
	writel(cfg, S5PC1XX_GPH3DAT);
	udelay(200);

	cfg |= (0x1 << 6);
	writel(cfg, S5PC1XX_GPH3DAT);
	udelay(2000);
#endif

	return 0;	
}

Example #4

Show file

/*
 * External camera reset
 * Because the most of cameras take i2c bus signal, so that
 * you have to reset at the boot time for other i2c slave devices.
 * Do optimization for cameras on your platform.
*/
static void smdkc100_reset_camera(void)
{
	void __iomem *regs = ioremap(S5PC1XX_PA_FIMC0, SZ_4K);
	u32 cfg;
	struct clk *clk = NULL;
	struct platform_device *pdev = &s3c_device_fimc0;

	clk = clk_get(&pdev->dev, "fimc");
	if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "failed to get fimc clock on reset camera\n");
		goto err_clk;
	}

	clk_enable(clk);
	/* based on s5k4ba at the channel A */
#if 0
	/* high reset */
	cfg = readl(regs + S3C_CIGCTRL);
	cfg |= S3C_CIGCTRL_CAMRST_A;
	writel(cfg, regs + S3C_CIGCTRL);
	udelay(200);

	cfg = readl(regs + S3C_CIGCTRL);
	cfg &= ~S3C_CIGCTRL_CAMRST_A;
	writel(cfg, regs + S3C_CIGCTRL);
	udelay(2000);
#else
	/* low reset */
	cfg = readl(regs + S3C_CIGCTRL);
	cfg &= ~S3C_CIGCTRL_CAMRST_A;
	writel(cfg, regs + S3C_CIGCTRL);
	udelay(200);

	cfg = readl(regs + S3C_CIGCTRL);
	cfg |= S3C_CIGCTRL_CAMRST_A;
	writel(cfg, regs + S3C_CIGCTRL);
	udelay(2000);
#endif

#if 0
	/* channel B reset: should be done by following after ch A reset */
	cfg = readl(S5PC1XX_GPH3CON);
	cfg &= ~S5PC1XX_GPH3_CONMASK(6);
	cfg |= S5PC1XX_GPH3_OUTPUT(6);
	writel(cfg, S5PC1XX_GPH3CON);

	cfg = readl(S5PC1XX_GPH3DAT);
	cfg &= ~(0x1 << 6);
	writel(cfg, S5PC1XX_GPH3DAT);
	udelay(200);

	cfg |= (0x1 << 6);
	writel(cfg, S5PC1XX_GPH3DAT);
	udelay(2000);
#endif

	clk_disable(clk);
	clk_put(clk);

err_clk:
	iounmap(regs);

}