void bt_uart_rts_ctrl(int flag)
{
unsigned int gpa0_bt_con;
unsigned int gpa0_bt_pud;
unsigned int gpa0_bt_dat;
if(flag)
{
// BT RTS Set to HIGH
s3c_gpio_cfgpin(S5PV210_GPA0(3), S3C_GPIO_OUTPUT);
s3c_gpio_setpull(S5PV210_GPA0(3), S3C_GPIO_PULL_NONE);
gpa0_bt_dat = __raw_readl(S5PV210_GPA0DAT);
gpa0_bt_dat |= (1 << 3);
__raw_writel(gpa0_bt_dat, S5PV210_GPA0DAT);
gpa0_bt_con = __raw_readl(S5PV210_GPA0CONPDN);
gpa0_bt_con |= (1 << 6);
gpa0_bt_con &= ~(1 << 7);
__raw_writel(gpa0_bt_con, S5PV210_GPA0CONPDN);
gpa0_bt_pud = __raw_readl(S5PV210_GPA0PUDPDN);
gpa0_bt_pud &= ~(1 << 7 | 1 << 6);
__raw_writel(gpa0_bt_pud, S5PV210_GPA0PUDPDN);
}
else
{
// BT RTS Set to LOW
s3c_gpio_cfgpin(S5PV210_GPA0(3), S3C_GPIO_OUTPUT);
gpa0_bt_dat = __raw_readl(S5PV210_GPA0DAT);
gpa0_bt_dat &= ~(1 << 3);
__raw_writel(gpa0_bt_dat, S5PV210_GPA0DAT);
s3c_gpio_cfgpin(S5PV210_GPA0(3), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5PV210_GPA0(3), S3C_GPIO_PULL_NONE);
}
}
void bt_uart_rts_ctrl(int flag)
{
if(!gpio_get_value(GPIO_BT_nRST))
return;
if(flag) {
// BT RTS Set to HIGH
s3c_gpio_cfgpin(S5PV210_GPA0(3), S3C_GPIO_OUTPUT);
s3c_gpio_setpull(S5PV210_GPA0(3), S3C_GPIO_PULL_NONE);
gpio_set_value(S5PV210_GPA0(3), 1);
s3c_gpio_slp_cfgpin(S5PV210_GPA0(3), S3C_GPIO_SLP_OUT0);
s3c_gpio_slp_setpull_updown(S5PV210_GPA0(3), S3C_GPIO_PULL_NONE);
}
else {
// BT RTS Set to LOW
s3c_gpio_cfgpin(S5PV210_GPA0(3), S3C_GPIO_OUTPUT);
gpio_set_value(S5PV210_GPA0(3), 0);
s3c_gpio_cfgpin(S5PV210_GPA0(3), S3C_GPIO_SFN(2));
s3c_gpio_setpull(S5PV210_GPA0(3), S3C_GPIO_PULL_NONE);
}
}
static struct regulator_init_data gpio_reg_gph26 = {
.constraints = {
.name = "VDD_BT/VDD_WLAN",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.state_mem = {
.mode = REGULATOR_MODE_NORMAL,
.enabled = 0,
},
},
.num_consumer_supplies = ARRAY_SIZE(gpio_reg_gph26_consumers),
.consumer_supplies = gpio_reg_gph26_consumers,
};
static struct gpio_regulator v210_gpio_regulators [] = {
[0] = { /*"VDD_GPS",*/
.gpio = S5PV210_GPA0(7),
.name = "LDO_GPA0(7)",
.type = GPIO_REGULATOR_VOLTAGE,
.initdata = &gpio_reg_gpa07,
},
[1] = { /*"VDD_CAM",*/
.gpio = S5PV210_GPB(3),
.name = "LDO_GPB(3)",
.type = GPIO_REGULATOR_VOLTAGE,
.initdata = &gpio_reg_gpb3,
},
[2] = { /*"VDD_5V",*/
.gpio = S5PV210_GPG1(6),
.name = "LDO_GPG1(6)",
.type = GPIO_REGULATOR_VOLTAGE,
.initdata = &gpio_reg_gpg16,
static int ams397g201_probe(struct device *dev)
{
int ret = 0;
struct regulator *r_lcd_1_8v, *r_lcd_3_0v, *r_lcd_1_1v;
lcd.bl_dev =backlight_device_register("s5p_bl",dev,&lcd,&s5p_bl_ops, NULL);
lcd.bl_dev->props.max_brightness = 255;
SetLDIEnabledFlag(1);
//For ESD test panel error
setup_timer(&polling_timer, polling_ESD_timer_func, 0);
mod_timer(&polling_timer,
jiffies + msecs_to_jiffies(5000));
#ifdef GAMMASET_CONTROL //for 1.9/2.2 gamma control from platform
gammaset_class = class_create(THIS_MODULE, "gammaset");
if (IS_ERR(gammaset_class))
pr_err("Failed to create class(gammaset_class)!\n");
switch_gammaset_dev = device_create(gammaset_class, NULL, 0, NULL, "switch_gammaset");
if (IS_ERR(switch_gammaset_dev))
pr_err("Failed to create device(switch_gammaset_dev)!\n");
if (device_create_file(switch_gammaset_dev, &dev_attr_gammaset_file_cmd) < 0)
pr_err("Failed to create device file(%s)!\n", dev_attr_gammaset_file_cmd.attr.name);
if (device_create_file(switch_gammaset_dev, &dev_attr_lcd_update) < 0)
pr_err("Failed to create device file(%s)!\n", dev_attr_lcd_update);
#endif
#ifdef ACL_ENABLE //ACL On,Off
acl_class = class_create(THIS_MODULE, "aclset");
if (IS_ERR(acl_class))
pr_err("Failed to create class(acl_class)!\n");
switch_aclset_dev = device_create(acl_class, NULL, 0, NULL, "switch_aclset");
if (IS_ERR(switch_aclset_dev))
pr_err("Failed to create device(switch_aclset_dev)!\n");
if (device_create_file(switch_aclset_dev, &dev_attr_aclset_file_cmd) < 0)
pr_err("Failed to create device file(%s)!\n", dev_attr_aclset_file_cmd.attr.name);
#endif
#if 1
//TE interrupt pin ( GPF0_1 /GPF0_INT[1] ) enable filter
s3c_gpio_int_flt(S5PV210_GPA0(0),1);
#define IRQ_TE_INT (IRQ_EINT_GROUP10_BASE+1) /* F0_1 */
/* irq for TE signal *///sehun_test
if (request_irq(/*S3C_GPIOINT(F0,1)*/IRQ_TE_INT, ams397g201_te_interrupt, IRQF_TRIGGER_RISING | IRQF_SHARED,
"te_signal", dev)) {
dev_err(dev, "request_irq failed.\n");
goto err_te_irq;
}
#if 1
/* irq for ESD signal */
s3c_gpio_cfgpin(S5PV210_GPH1(2), S3C_GPIO_SFN(0xFF));
s3c_gpio_setpull(S5PV210_GPH1(2), S3C_GPIO_PULL_UP);
set_irq_type(LCD_ESD_INT, IRQ_TYPE_EDGE_RISING);
if( (ret = request_irq(LCD_ESD_INT, ams397g201_esd_irq_handler,IRQF_DISABLED , "LCD_ESD", NULL)) < 0 )
{
printk("%s, request_irq failed %d, ret= %d\n",__FUNCTION__, LCD_ESD_INT, ret );
}
disable_irq( LCD_ESD_INT);
mdelay(10);
//enable_irq( LCD_ESD_INT);
#endif
#endif
r_lcd_1_8v = regulator_get(dev, "vlcd");
if (IS_ERR(r_lcd_1_8v)) {
dev_err(dev, "failed to get regulator vlcd.\n");
return -EINVAL;
}
r_lcd_1_1v = regulator_get(dev, "VMIPI_1.8V");
if (IS_ERR(r_lcd_1_1v)) {
dev_err(dev, "failed to get regulator VMIPI_1.8V.\n");
return -EINVAL;
}
regulator_enable(r_lcd_1_1v);
r_lcd_1_1v = regulator_get(dev, "VMIPI_1.1V");
if (IS_ERR(r_lcd_1_1v)) {
dev_err(dev, "failed to get regulator VMIPI_1.1V.\n");
return -EINVAL;
}
regulator_enable(r_lcd_1_1v);
#if 0
ret = regulator_set_voltage(r_lcd_1_8v, 1800000, 1800000);
if(ret != 0) {
printk(KERN_ERR "%s: Cannot set VLCD_1.8V\n", __func__);
return -EINVAL;
}
ret = regulator_enable(r_lcd_1_8v);
if (ret < 0) {
printk(KERN_ERR "failed to enable regulator VLCD_1_8v.\n");
return ret;
}
#endif
r_lcd_3_0v = regulator_get(dev, "vcc_lcd");
if (IS_ERR(r_lcd_3_0v)) {
dev_err(dev, "failed to get regulator vcc_lcd.\n");
return -EINVAL;
}
#if 0
ret = regulator_set_voltage(r_lcd_3_0v, 3000000, 3000000);
if(ret != 0) {
printk(KERN_ERR "%s: Cannot set VLCD_3.0V\n", __func__);
return -EINVAL;
}
ret = regulator_enable(r_lcd_3_0v);
if (ret < 0) {
printk(KERN_ERR "failed to enable regulator VLCD_3_0v.\n");
return ret;
}
#endif
#if 0 //@@
/* lcd power on */
if (ddi_pd->lcd_power_on)
ddi_pd->lcd_power_on((void *) dev, 1);
else
dev_warn(dev, "lcd_power_on func is null.\n");
mdelay(60);
/* lcd reset */
if (ddi_pd->lcd_reset)
ddi_pd->lcd_reset();
else
dev_warn(dev, "lcd_reset func is null.\n");
#endif
dev_info(dev, "ams397g201 lcd panel driver based on mipi-dsi has been probed.\n");
err_te_irq:
return 0;
}
.set_pin = s3c_gpio_setpin_updown,
};
static struct s3c_gpio_cfg gpio_cfg_noint = {
.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
.set_pull = s3c_gpio_setpull_updown,
.get_pull = s3c_gpio_getpull_updown,
.set_pin = s3c_gpio_setpin_updown,
};
static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
{
.base = S5PV210_GPA0_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PV210_GPA0(0),
.ngpio = S5PV210_GPIO_A0_NR,
.label = "GPA0",
},
}, {
.base = S5PV210_GPA1_BASE,
.config = &gpio_cfg,
.chip = {
.base = S5PV210_GPA1(0),
.ngpio = S5PV210_GPIO_A1_NR,
.label = "GPA1",
},
}, {
.base = S5PV210_GPB_BASE,
.config = &gpio_cfg,
.chip = {
static void s5pv210_uart_init(struct uart_t * uart)
{
struct resource_t * res = (struct resource_t *)uart->priv;
struct s5pv210_uart_data_t * dat = (struct s5pv210_uart_data_t *)res->data;
switch(res->id)
{
case 0:
clk_enable("psys-pclk");
/* Configure GPA01, GPA00 for TXD0, RXD0 and pull up */
gpio_set_cfg(S5PV210_GPA0(1), 0x2);
gpio_set_cfg(S5PV210_GPA0(0), 0x2);
gpio_set_pull(S5PV210_GPA0(1), GPIO_PULL_UP);
gpio_set_pull(S5PV210_GPA0(0), GPIO_PULL_UP);
write32(dat->regbase + S5PV210_UCON, 0x00000005);
write32(dat->regbase + S5PV210_UFCON, 0x00000777);
write32(dat->regbase + S5PV210_UMON, 0x00000000);
break;
case 1:
clk_enable("psys-pclk");
/* Configure GPA05, GPA04 for TXD1, RXD1 */
gpio_set_cfg(S5PV210_GPA0(5), 0x2);
gpio_set_cfg(S5PV210_GPA0(4), 0x2);
gpio_set_pull(S5PV210_GPA0(5), GPIO_PULL_UP);
gpio_set_pull(S5PV210_GPA0(4), GPIO_PULL_UP);
write32(dat->regbase + S5PV210_UCON, 0x00000005);
write32(dat->regbase + S5PV210_UFCON, 0x00000777);
write32(dat->regbase + S5PV210_UMON, 0x00000000);
break;
case 2:
clk_enable("psys-pclk");
/* Configure GPA11, GPA10 for TXD2, RXD2 */
gpio_set_cfg(S5PV210_GPA1(1), 0x2);
gpio_set_cfg(S5PV210_GPA1(0), 0x2);
gpio_set_pull(S5PV210_GPA1(1), GPIO_PULL_UP);
gpio_set_pull(S5PV210_GPA1(0), GPIO_PULL_UP);
write32(dat->regbase + S5PV210_UCON, 0x00000005);
write32(dat->regbase + S5PV210_UFCON, 0x00000777);
break;
case 3:
clk_enable("psys-pclk");
/* Configure GPA13, GPA12 for TXD3, RXD3 */
gpio_set_cfg(S5PV210_GPA1(3), 0x2);
gpio_set_cfg(S5PV210_GPA1(2), 0x2);
gpio_set_pull(S5PV210_GPA1(3), GPIO_PULL_UP);
gpio_set_pull(S5PV210_GPA1(2), GPIO_PULL_UP);
write32(dat->regbase + S5PV210_UCON, 0x00000005);
write32(dat->regbase + S5PV210_UFCON, 0x00000777);
break;
default:
return;
}
s5pv210_uart_setup(uart, dat->baud, dat->data, dat->parity, dat->stop);
}
