static void s5p_irq_eint_unmask(struct irq_data *data) { u32 mask; mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq))); mask &= ~(eint_irq_to_bit(data->irq)); __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq))); }
static void s5p_irq_eint_unmask(unsigned int irq) { u32 mask; mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq))); mask &= ~(eint_irq_to_bit(irq)); __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq))); }
static void exynos4_irq_eint_unmask(struct irq_data *data) { u32 mask; spin_lock(&eint_lock); mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq))); mask &= ~(eint_irq_to_bit(data->irq)); __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq))); spin_unlock(&eint_lock); }
static void s5pv310_irq_eint_unmask(unsigned int irq) { u32 mask; spin_lock(&eint_lock); mask = __raw_readl(S5P_EINT_MASK(s5pv310_irq_split(irq))); mask &= ~(s5pv310_irq_to_bit(irq)); __raw_writel(mask, S5P_EINT_MASK(s5pv310_irq_split(irq))); spin_unlock(&eint_lock); }
static void s5p_irq_eint_unmask(struct irq_data *data) { u32 mask; /* for level triggered interrupts, masking doesn't prevent * the interrupt from becoming pending again. by the time * the handler (either irq or thread) can do its thing to clear * the interrupt, it's too late because it could be pending * already. we have to ack it here, after the handler runs, * or else we get a false interrupt. */ if (irqd_is_level_type(data)) s5p_irq_eint_ack(data); mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq))); mask &= ~(eint_irq_to_bit(data->irq)); __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq))); }
/* s5p_irq_demux_eint * * This function demuxes the IRQ from the group0 external interrupts, * from EINTs 16 to 31. It is designed to be inlined into the specific * handler s5p_irq_demux_eintX_Y. * * Each EINT pend/mask registers handle eight of them. */ static inline void s5p_irq_demux_eint(unsigned int start) { u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start))); u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start))); unsigned int irq; status &= ~mask; status &= 0xff; while (status) { irq = fls(status) - 1; generic_handle_irq(irq + start); status &= ~(1 << irq); } }
unsigned int universal_sdhci2_detect_ext_cd(void) { unsigned int card_status = 0; #ifdef CONFIG_MMC_DEBUG printk(KERN_DEBUG "Universal :SD Detect function\n"); printk(KERN_DEBUG "eint conf %x eint filter conf %x", readl(S5P_EINT_CON(3)), readl(S5P_EINT_FLTCON(3, 1))); printk(KERN_DEBUG "eint pend %x eint mask %x", readl(S5P_EINT_PEND(3)), readl(S5P_EINT_MASK(3))); #endif card_status = gpio_get_value(S5PV210_GPH3(4)); printk(KERN_DEBUG "Universal : Card status %d\n", card_status ? 0 : 1); return card_status ? 0 : 1; }
unsigned int universal_sdhci2_detect_ext_cd(void) { unsigned int card_status = 0; #ifdef CONFIG_MMC_DEBUG printk(KERN_DEBUG "Universal :SD Detect function\n"); printk(KERN_DEBUG "eint conf %x eint filter conf %x", readl(S5P_EINT_CON(3)), readl(S5P_EINT_FLTCON(3, 1))); printk(KERN_DEBUG "eint pend %x eint mask %x", readl(S5P_EINT_PEND(3)), readl(S5P_EINT_MASK(3))); #endif card_status = gpio_get_value(GPIO_T_FLASH_DETECT) ? 0 : 1; /* active low */ printk(KERN_DEBUG " Universal: Card status %s\n", card_status ? "inserted" : "removed"); return card_status; }
/* s5pv310_irq_demux_eint * * This function demuxes the IRQ from the group0 external interrupts, * from EINTs 16 to 31. It is designed to be inlined into the specific * handler s5p_irq_demux_eintX_Y. * * Each EINT pend/mask registers handle eight of them. */ static inline u32 s5pv310_irq_demux_eint(unsigned int irq, unsigned int start) { unsigned int cascade_irq; u32 status = __raw_readl(S5P_EINT_PEND(s5pv310_irq_split(start))); u32 mask = __raw_readl(S5P_EINT_MASK(s5pv310_irq_split(start))); u32 action = 0; status &= ~mask; status &= 0xff; while (status) { cascade_irq = fls(status) - 1; generic_handle_irq(cascade_irq + start); status &= ~(1 << cascade_irq); ++action; } return action; }
/* exynos_irq_demux_eint * * This function demuxes the IRQ from from EINTs 16 to 31. * It is designed to be inlined into the specific handler * s5p_irq_demux_eintX_Y. * * Each EINT pend/mask registers handle eight of them. */ static inline u32 exynos_irq_demux_eint(unsigned int start) { unsigned int irq; u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start))); u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start))); u32 action = 0; status &= ~mask; status &= 0xff; while (status) { irq = fls(status) - 1; generic_handle_irq(irq + start); status &= ~(1 << irq); ++action; } return action; }
#if TO_DO SAVE_ITEM(S5P_EINT_CON(0)), SAVE_ITEM(S5P_EINT_CON(1)), SAVE_ITEM(S5P_EINT_CON(2)), SAVE_ITEM(S5P_EINT_CON(3)), SAVE_ITEM(S5P_EINT_FLTCON(0)), SAVE_ITEM(S5P_EINT_FLTCON(1)), SAVE_ITEM(S5P_EINT_FLTCON(2)), SAVE_ITEM(S5P_EINT_FLTCON(3)), SAVE_ITEM(S5P_EINT_FLTCON(4)), SAVE_ITEM(S5P_EINT_FLTCON(5)), SAVE_ITEM(S5P_EINT_FLTCON(6)), SAVE_ITEM(S5P_EINT_FLTCON(7)), SAVE_ITEM(S5P_EINT_MASK(0)), SAVE_ITEM(S5P_EINT_MASK(1)), SAVE_ITEM(S5P_EINT_MASK(2)), SAVE_ITEM(S5P_EINT_MASK(3)), #endif }; int s3c24xx_irq_suspend(void) { s3c_pm_do_save(eint_save, ARRAY_SIZE(eint_save)); return 0; } void s3c24xx_irq_resume(void) {