int main(void)
{
int i, j, samples[] = {190, 191, 192, 193, 379, 380, 381, 382};
char s[1024];
DEF_GENPAT("circuit");
/* interface */
DECLAR("ck", ":1", "B", IN, "", "");
DECLAR("d", ":1", "B", IN, "", "");
DECLAR("o", ":1", "B", OUT, "0 to 22", "");
DECLAR("vddi", ":2", "B", IN, "", "");
DECLAR("vssi", ":2", "B", IN, "", "");
DECLAR("vdde", ":2", "B", IN, "", "");
DECLAR("vsse", ":2", "B", IN, "", "");
LABEL("tuner");
SETTUNIT("ns");
AFFECT("0", "ck", "0b0");
AFFECT("0", "d", "0b0");
AFFECT("0", "vddi", "0b1");
AFFECT("0", "vssi", "0b0");
AFFECT("0", "vdde", "0b1");
AFFECT("0", "vsse", "0b0");
for (j = 0; j < ARRAY_SIZE(samples); j++) {
int n = 0;
AFFECT("+10", "ck", "0b1"); n++;
AFFECT("+10", "d", "0b1");
AFFECT("+0", "ck", "0b0");
AFFECT("+10", "ck", "0b1"); n++;
AFFECT("+10", "d", "0b0");
AFFECT("+0", "ck", "0b0");
for (i = 0; i < samples[j] - n; i++) {
AFFECT("+10", "ck", "0b1");
AFFECT("+10", "ck", "0b0");
}
}
SAV_GENPAT();
}
int main() {
FILE *arq = NULL;
char patFilename[] = __FILE__;
patFilename[ strlen(patFilename)-2 ] = '\0';
arq = fopen("instructions/control.txt", "r+");
if( !arq ) {
fprintf(stderr, "\nCouldn't open 'instructions/control.txt' file.\n");
return 1;
}
DEF_GENPAT(patFilename);
DECLAR("CLK" , ":2", "B", IN , "", "");
DECLAR("Reset" , ":2", "B", IN , "","");
DECLAR("State" , ":2", "X", OUT, "3 down to 0", "");
DECLAR("Opcode" , ":2", "B", IN , "5 down to 0", "");
// Multiplexer Selects
DECLAR("MemtoReg" , ":2", "B", OUT, "", "");
DECLAR("RegDst" , ":2", "B", OUT, "", "");
DECLAR("IorD" , ":2", "B", OUT, "", "");
DECLAR("PCSrc" , ":2", "B", OUT, "1 down to 0", "");
DECLAR("ALUSrcA" , ":2", "B", OUT, "", "");
DECLAR("ALUSrcB" , ":2", "B", OUT, "1 down to 0", "");
DECLAR("ALUOp" , ":2", "B", OUT, "1 down to 0", "");
// Registers Enables
DECLAR("IRWrite" , ":2", "B", OUT, "", "");
DECLAR("MemWrite" , ":2", "B", OUT, "", "");
DECLAR("PCWrite" , ":2", "B", OUT, "", "");
DECLAR("RegWrite" , ":2", "B", OUT, "", "");
DECLAR("Branch" , ":2", "B", OUT, "", "");
DECLAR ("Vdd" , ":2", "B", IN , "", "");
DECLAR ("Vss" , ":2", "B", IN , "", "");
AFFECT ("0", "Vdd", "1");
AFFECT ("0", "Vss", "0");
AFFECT ("0", "CLK", "0");
AFFECT ("0", "Reset", "1");
AFFECT ("0", "Opcode", "0");
FsmMode = MODE_FSM;
curvect++;
toggleClock();
FsmReset();
curvect++;
toggleClock();
AFFECT (cvect(), "Reset", "0");
curvect++;
while(1) {
toggleClock();
FsmRunState();
curvect++;
toggleClock();
if(FsmNextState == 1) {
if( !getNextInstr(arq) ) {
break;
}
AFFECT(cvect(), "Opcode", inttostr(DecOpcode));
FsmOpcode = DecOpcode;
}
curvect++;
}
SAV_GENPAT();
return 0;
}
int main () {
DEF_GENPAT("dpt_regfile_genpat");
// endereços de entrada
DECLAR("CLK", ":2", "B", IN , "", "");
DECLAR("A3" , ":2", "X", IN , "4 down to 0" , "");
DECLAR("WD3", ":2", "X", IN , "31 down to 0", "");
DECLAR("WE3", ":2", "B", IN , "", "");
DECLAR("A1" , ":2", "X", IN , "4 down to 0" , "");
DECLAR("RD1", ":2", "X", OUT, "31 down to 0", "");
DECLAR("A2" , ":2", "X", IN , "4 down to 0" , "");
DECLAR("RD2", ":2", "X", OUT, "31 down to 0", "");
DECLAR("Vdd", ":2", "B", IN , "", "" );
DECLAR("Vss", ":2", "B", IN , "", "" );
LABEL ("regfile");
AFFECT(cvect(), "Vdd", "0b1");
AFFECT(cvect(), "Vss", "0b0");
AFFECT(cvect(), "CLK", inttostr(CLK));
RegInit();
RegAffect();
RegA3 = 0;
RegWD3 = 0xFFFFFFFF;
RegWE3 = 1;
RegAffect();
curvect++;
toggleClock();
RegWrite();
curvect++;
toggleClock();
int reg;
for(reg = 1; reg < 32; reg++) {
RegA1 = reg - 1;
RegA2 = reg;
RegA3 = reg;
RegWD3 = 0x00000000;
RegWE3 = 1;
RegAffect();
curvect++; toggleClock();
RegWrite();
curvect++; toggleClock();
RegWD3 = 0xFFFFFFFF;
RegWE3 = 0;
RegAffect();
curvect++; toggleClock();
RegWrite();
curvect++; toggleClock();
RegWE3 = 1;
RegAffect();
curvect++; toggleClock();
RegWrite();
curvect++; toggleClock();
RegWD3 = 0x00000000;
RegWE3 = 0;
RegAffect();
curvect++; toggleClock();
RegWrite();
curvect++; toggleClock();
RegWE3 = 1;
RegAffect();
curvect++; toggleClock();
RegWrite();
curvect++; toggleClock();
if(reg % 2 == 1) {
RegWD3 = 0xFFFFFFFF;
RegWE3 = 1;
RegAffect();
curvect++; toggleClock();
RegWrite();
curvect++; toggleClock();
}
}
SAV_GENPAT ();
return 0;
}
int main () {
int i;
srand(time(NULL));
DEF_GENPAT("dpt_alu_genpat");
DECLAR("A" , ":2", "X", IN , "31 down to 0", "");
DECLAR("B" , ":2", "X", IN , "31 down to 0", "");
DECLAR("Ctrl", ":2", "X", IN , "2 down to 0", "");
DECLAR("Res" , ":2", "X", OUT, "31 down to 0", "");
DECLAR("Zero", ":2", "B", OUT, "", "" );
DECLAR("Vdd" , ":2", "B", IN , "", "" );
DECLAR("Vss" , ":2", "B", IN , "", "" );
LABEL ("ALU");
AFFECT("0", "Vdd", "0b1");
AFFECT("0", "Vss", "0b0");
// AND : Ctrl = 0
ALU(0x00000000, 0x00000000, 0);
ALU(0x00000000, 0xFFFFFFFF, 0);
ALU(0xFFFFFFFF, 0x00000000, 0);
ALU(0xFFFFFFFF, 0xFFFFFFFF, 0);
// OR : Ctrl = 1
ALU(0x00000000, 0x00000000, 1);
ALU(0x00000000, 0xFFFFFFFF, 1);
ALU(0xFFFFFFFF, 0x00000000, 1);
ALU(0xFFFFFFFF, 0xFFFFFFFF, 1);
// add : ctrl = 2 (0b010)
ALU(0xFFFFFFFF, 1, 2); // test all carry bits, overflow and zero flag
for(i = 0; i < 10; i++) {
ALU(rand(), rand(), 2);
}
// A AND ~B : Ctrl = 4
ALU(0x00000000, 0x00000000, 4);
ALU(0x00000000, 0xFFFFFFFF, 4);
ALU(0xFFFFFFFF, 0x00000000, 4);
ALU(0xFFFFFFFF, 0xFFFFFFFF, 4);
// A OR ~B : Ctrl = 5
ALU(0x00000000, 0x00000000, 5);
ALU(0x00000000, 0xFFFFFFFF, 5);
ALU(0xFFFFFFFF, 0x00000000, 5);
ALU(0xFFFFFFFF, 0xFFFFFFFF, 5);
// sub : ctrl = 6 (0b110)
ALU(0x0F0F0F0F, 0x00F00F00, 6);
ALU(0xFFFFFFFF, 0xFFFFFFFF, 6);
ALU(0x00000000, 0x00000001, 6);
for(i = 0; i < 10; i++) {
ALU(rand(), rand(), 6);
}
// slt : ctrl = 7 (0b111)
ALU(-300, 255, 7);
ALU(25, -30, 7);
for(i = 0; i < 10; i++) {
ALU(rand(), rand(), 7);
}
SAV_GENPAT();
return 0;
}
