/* Control Register Constants */
#define BWTWO_CTL_ENABLE_INTS 0x80
#define BWTWO_CTL_ENABLE_VIDEO 0x40
#define BWTWO_CTL_ENABLE_TIMING 0x20
#define BWTWO_CTL_ENABLE_CURCMP 0x10
#define BWTWO_CTL_XTAL_MASK 0x0C
#define BWTWO_CTL_DIVISOR_MASK 0x03
/* Status Register Constants */
#define BWTWO_STAT_PENDING_INT 0x80
#define BWTWO_STAT_MSENSE_MASK 0x70
#define BWTWO_STAT_ID_MASK 0x0f
static struct sbus_mmap_map bw2_mmap_map[] = {
{ 0, 0, SBUS_MMAP_FBSIZE(1) },
{ 0, 0, 0 }
};
static void bw2_blank (struct fb_info_sbusfb *fb)
{
unsigned long flags;
u8 tmp;
spin_lock_irqsave(&fb->lock, flags);
tmp = sbus_readb(&fb->s.bw2.regs->control);
tmp &= ~BWTWO_CTL_ENABLE_VIDEO;
sbus_writeb(tmp, &fb->s.bw2.regs->control);
spin_unlock_irqrestore(&fb->lock, flags);
}
volatile u8 comp_sync_end;
volatile u8 v_blank_start_high;
volatile u8 v_blank_start_low;
volatile u8 v_blank_end;
volatile u8 v_sync_start;
volatile u8 v_sync_end;
volatile u8 xfer_holdoff_start;
volatile u8 xfer_holdoff_end;
};
/* Offset of interesting structures in the OBIO space */
#define CG3_REGS_OFFSET 0x400000UL
#define CG3_RAM_OFFSET 0x800000UL
static struct sbus_mmap_map cg3_mmap_map[] = {
{ CG3_MMAP_OFFSET, CG3_RAM_OFFSET, SBUS_MMAP_FBSIZE(1) },
{ 0, 0, 0 }
};
/* The cg3 palette is loaded with 4 color values at each time */
/* so you end up with: (rgb)(r), (gb)(rg), (b)(rgb), and so on */
#define D4M3(x) ((((x)>>2)<<1) + ((x)>>2)) /* (x/4)*3 */
#define D4M4(x) ((x)&~0x3) /* (x/4)*4 */
static void cg3_loadcmap (struct fb_info_sbusfb *fb, struct display *p, int index, int count)
{
struct bt_regs *bt = &fb->s.cg3.regs->cmap;
unsigned long flags;
u32 *i;
volatile u8 *regp;
u32 thc_pad0[511];
volatile u32 thc_hs; /* hsync timing */
volatile u32 thc_hsdvs;
volatile u32 thc_hd;
volatile u32 thc_vs; /* vsync timing */
volatile u32 thc_vd;
volatile u32 thc_refresh;
volatile u32 thc_misc;
u32 thc_pad1[56];
volatile u32 thc_cursxy; /* cursor x,y position (16 bits each) */
volatile u32 thc_cursmask[32]; /* cursor mask bits */
volatile u32 thc_cursbits[32]; /* what to show where mask enabled */
};
static struct sbus_mmap_map tcx_mmap_map[] = {
{ TCX_RAM8BIT, 0, SBUS_MMAP_FBSIZE(1) },
{ TCX_RAM24BIT, 0, SBUS_MMAP_FBSIZE(4) },
{ TCX_UNK3, 0, SBUS_MMAP_FBSIZE(8) },
{ TCX_UNK4, 0, SBUS_MMAP_FBSIZE(8) },
{ TCX_CONTROLPLANE, 0, SBUS_MMAP_FBSIZE(4) },
{ TCX_UNK6, 0, SBUS_MMAP_FBSIZE(8) },
{ TCX_UNK7, 0, SBUS_MMAP_FBSIZE(8) },
{ TCX_TEC, 0, PAGE_SIZE },
{ TCX_BTREGS, 0, PAGE_SIZE },
{ TCX_THC, 0, PAGE_SIZE },
{ TCX_DHC, 0, PAGE_SIZE },
{ TCX_ALT, 0, PAGE_SIZE },
{ TCX_UNK2, 0, 0x20000 },
{ 0, 0, 0 }
};
