static void scc_spcond_int(int irq, void *data, struct pt_regs *fp)
{
struct scc_port *port = data;
struct tty_struct *tty = port->gs.tty;
unsigned char stat, ch, err;
int int_pending_mask = port->channel == CHANNEL_A ?
IPR_A_RX : IPR_B_RX;
SCC_ACCESS_INIT(port);
if (!tty) {
printk(KERN_WARNING "scc_spcond_int with NULL tty!\n");
SCCwrite(COMMAND_REG, CR_ERROR_RESET);
SCCwrite_NB(COMMAND_REG, CR_HIGHEST_IUS_RESET);
return;
}
do {
stat = SCCread(SPCOND_STATUS_REG);
ch = SCCread_NB(RX_DATA_REG);
if (stat & SCSR_RX_OVERRUN)
err = TTY_OVERRUN;
else if (stat & SCSR_PARITY_ERR)
err = TTY_PARITY;
else if (stat & SCSR_CRC_FRAME_ERR)
err = TTY_FRAME;
else
err = 0;
if (tty->flip.count < TTY_FLIPBUF_SIZE) {
*tty->flip.char_buf_ptr = ch;
*tty->flip.flag_buf_ptr = err;
tty->flip.flag_buf_ptr++;
tty->flip.char_buf_ptr++;
tty->flip.count++;
}
/* ++TeSche: *All* errors have to be cleared manually,
* else the condition persists for the next chars
*/
if (err)
SCCwrite(COMMAND_REG, CR_ERROR_RESET);
} while(SCCread(INT_PENDING_REG) & int_pending_mask);
SCCwrite_NB(COMMAND_REG, CR_HIGHEST_IUS_RESET);
tty_flip_buffer_push(tty);
}
static int scc_chars_in_buffer (void *ptr)
{
struct scc_port *port = ptr;
SCC_ACCESS_INIT(port);
return (SCCread (SPCOND_STATUS_REG) & SCSR_ALL_SENT) ? 0 : 1;
}
static irqreturn_t scc_rx_int(int irq, void *data)
{
unsigned char ch;
struct scc_port *port = data;
struct tty_struct *tty = port->gs.port.tty;
SCC_ACCESS_INIT(port);
ch = SCCread_NB(RX_DATA_REG);
if (!tty) {
printk(KERN_WARNING "scc_rx_int with NULL tty!\n");
SCCwrite_NB(COMMAND_REG, CR_HIGHEST_IUS_RESET);
return IRQ_HANDLED;
}
tty_insert_flip_char(tty, ch, 0);
/* Check if another character is already ready; in that case, the
* spcond_int() function must be used, because this character may have an
* error condition that isn't signalled by the interrupt vector used!
*/
if (SCCread(INT_PENDING_REG) &
(port->channel == CHANNEL_A ? IPR_A_RX : IPR_B_RX)) {
scc_spcond_int (irq, data);
return IRQ_HANDLED;
}
SCCwrite_NB(COMMAND_REG, CR_HIGHEST_IUS_RESET);
tty_flip_buffer_push(tty);
return IRQ_HANDLED;
}
static void scc_rx_int(int irq, void *data, struct pt_regs *fp)
{
unsigned char ch;
struct scc_port *port = data;
struct tty_struct *tty = port->gs.tty;
SCC_ACCESS_INIT(port);
ch = SCCread_NB(RX_DATA_REG);
if (!tty) {
printk(KERN_WARNING "scc_rx_int with NULL tty!\n");
SCCwrite_NB(COMMAND_REG, CR_HIGHEST_IUS_RESET);
return;
}
if (tty->flip.count < TTY_FLIPBUF_SIZE) {
*tty->flip.char_buf_ptr = ch;
*tty->flip.flag_buf_ptr = 0;
tty->flip.flag_buf_ptr++;
tty->flip.char_buf_ptr++;
tty->flip.count++;
}
/* Check if another character is already ready; in that case, the
* spcond_int() function must be used, because this character may have an
* error condition that isn't signalled by the interrupt vector used!
*/
if (SCCread(INT_PENDING_REG) &
(port->channel == CHANNEL_A ? IPR_A_RX : IPR_B_RX)) {
scc_spcond_int (irq, data, fp);
return;
}
SCCwrite_NB(COMMAND_REG, CR_HIGHEST_IUS_RESET);
tty_flip_buffer_push(tty);
}
static void scc_setsignals(struct scc_port *port, int dtr, int rts)
{
unsigned long flags;
unsigned char t;
SCC_ACCESS_INIT(port);
local_irq_save(flags);
t = SCCread(TX_CTRL_REG);
if (dtr >= 0) t = dtr? (t | TCR_DTR): (t & ~TCR_DTR);
if (rts >= 0) t = rts? (t | TCR_RTS): (t & ~TCR_RTS);
SCCwrite(TX_CTRL_REG, t);
local_irq_restore(flags);
}
static int scc_open (struct tty_struct * tty, struct file * filp)
{
int line = tty->index;
int retval;
struct scc_port *port = &scc_ports[line];
int i, channel = port->channel;
unsigned long flags;
SCC_ACCESS_INIT(port);
#if defined(CONFIG_MVME162_SCC) || defined(CONFIG_MVME147_SCC)
static const struct {
unsigned reg, val;
} mvme_init_tab[] = {
/* Values for MVME162 and MVME147 */
/* no parity, 1 stop bit, async, 1:16 */
{ AUX1_CTRL_REG, A1CR_PARITY_NONE|A1CR_MODE_ASYNC_1|A1CR_CLKMODE_x16 },
/* parity error is special cond, ints disabled, no DMA */
{ INT_AND_DMA_REG, IDR_PARERR_AS_SPCOND | IDR_RX_INT_DISAB },
/* Rx 8 bits/char, no auto enable, Rx off */
{ RX_CTRL_REG, RCR_CHSIZE_8 },
/* DTR off, Tx 8 bits/char, RTS off, Tx off */
{ TX_CTRL_REG, TCR_CHSIZE_8 },
/* special features off */
{ AUX2_CTRL_REG, 0 },
{ CLK_CTRL_REG, CCR_RXCLK_BRG | CCR_TXCLK_BRG },
{ DPLL_CTRL_REG, DCR_BRG_ENAB | DCR_BRG_USE_PCLK },
/* Start Rx */
{ RX_CTRL_REG, RCR_RX_ENAB | RCR_CHSIZE_8 },
/* Start Tx */
{ TX_CTRL_REG, TCR_TX_ENAB | TCR_RTS | TCR_DTR | TCR_CHSIZE_8 },
/* Ext/Stat ints: DCD only */
{ INT_CTRL_REG, ICR_ENAB_DCD_INT },
/* Reset Ext/Stat ints */
{ COMMAND_REG, CR_EXTSTAT_RESET },
/* ...again */
{ COMMAND_REG, CR_EXTSTAT_RESET },
};
#endif
#if defined(CONFIG_BVME6000_SCC)
static const struct {
unsigned reg, val;
} bvme_init_tab[] = {
/* Values for BVME6000 */
/* no parity, 1 stop bit, async, 1:16 */
{ AUX1_CTRL_REG, A1CR_PARITY_NONE|A1CR_MODE_ASYNC_1|A1CR_CLKMODE_x16 },
/* parity error is special cond, ints disabled, no DMA */
{ INT_AND_DMA_REG, IDR_PARERR_AS_SPCOND | IDR_RX_INT_DISAB },
/* Rx 8 bits/char, no auto enable, Rx off */
{ RX_CTRL_REG, RCR_CHSIZE_8 },
/* DTR off, Tx 8 bits/char, RTS off, Tx off */
{ TX_CTRL_REG, TCR_CHSIZE_8 },
/* special features off */
{ AUX2_CTRL_REG, 0 },
{ CLK_CTRL_REG, CCR_RTxC_XTAL | CCR_RXCLK_BRG | CCR_TXCLK_BRG },
{ DPLL_CTRL_REG, DCR_BRG_ENAB },
/* Start Rx */
{ RX_CTRL_REG, RCR_RX_ENAB | RCR_CHSIZE_8 },
/* Start Tx */
{ TX_CTRL_REG, TCR_TX_ENAB | TCR_RTS | TCR_DTR | TCR_CHSIZE_8 },
/* Ext/Stat ints: DCD only */
{ INT_CTRL_REG, ICR_ENAB_DCD_INT },
/* Reset Ext/Stat ints */
{ COMMAND_REG, CR_EXTSTAT_RESET },
/* ...again */
{ COMMAND_REG, CR_EXTSTAT_RESET },
};
#endif
if (!(port->gs.port.flags & ASYNC_INITIALIZED)) {
local_irq_save(flags);
#if defined(CONFIG_MVME147_SCC) || defined(CONFIG_MVME162_SCC)
if (MACH_IS_MVME147 || MACH_IS_MVME16x) {
for (i = 0; i < ARRAY_SIZE(mvme_init_tab); ++i)
SCCwrite(mvme_init_tab[i].reg, mvme_init_tab[i].val);
}
#endif
#if defined(CONFIG_BVME6000_SCC)
if (MACH_IS_BVME6000) {
for (i = 0; i < ARRAY_SIZE(bvme_init_tab); ++i)
SCCwrite(bvme_init_tab[i].reg, bvme_init_tab[i].val);
}
#endif
/* remember status register for detection of DCD and CTS changes */
scc_last_status_reg[channel] = SCCread(STATUS_REG);
port->c_dcd = 0; /* Prevent initial 1->0 interrupt */
scc_setsignals (port, 1,1);
local_irq_restore(flags);
}
tty->driver_data = port;
port->gs.port.tty = tty;
port->gs.port.count++;
retval = gs_init_port(&port->gs);
if (retval) {
port->gs.port.count--;
return retval;
}
port->gs.port.flags |= GS_ACTIVE;
retval = gs_block_til_ready(port, filp);
if (retval) {
port->gs.port.count--;
return retval;
}
port->c_dcd = tty_port_carrier_raised(&port->gs.port);
scc_enable_rx_interrupts(port);
return 0;
}
static int scc_open (struct tty_struct * tty, struct file * filp)
{
int line = MINOR(tty->device) - SCC_MINOR_BASE;
int retval;
struct scc_port *port = &scc_ports[line];
int i, channel = port->channel;
unsigned long flags;
SCC_ACCESS_INIT(port);
#if defined(CONFIG_MVME162_SCC) || defined(CONFIG_MVME147_SCC)
static const struct {
unsigned reg, val;
} mvme_init_tab[] = {
/* Values for MVME162 and MVME147 */
/* no parity, 1 stop bit, async, 1:16 */
{ AUX1_CTRL_REG, A1CR_PARITY_NONE|A1CR_MODE_ASYNC_1|A1CR_CLKMODE_x16 },
/* parity error is special cond, ints disabled, no DMA */
{ INT_AND_DMA_REG, IDR_PARERR_AS_SPCOND | IDR_RX_INT_DISAB },
/* Rx 8 bits/char, no auto enable, Rx off */
{ RX_CTRL_REG, RCR_CHSIZE_8 },
/* DTR off, Tx 8 bits/char, RTS off, Tx off */
{ TX_CTRL_REG, TCR_CHSIZE_8 },
/* special features off */
{ AUX2_CTRL_REG, 0 },
{ CLK_CTRL_REG, CCR_RXCLK_BRG | CCR_TXCLK_BRG },
{ DPLL_CTRL_REG, DCR_BRG_ENAB | DCR_BRG_USE_PCLK },
/* Start Rx */
{ RX_CTRL_REG, RCR_RX_ENAB | RCR_CHSIZE_8 },
/* Start Tx */
{ TX_CTRL_REG, TCR_TX_ENAB | TCR_RTS | TCR_DTR | TCR_CHSIZE_8 },
/* Ext/Stat ints: DCD only */
{ INT_CTRL_REG, ICR_ENAB_DCD_INT },
/* Reset Ext/Stat ints */
{ COMMAND_REG, CR_EXTSTAT_RESET },
/* ...again */
{ COMMAND_REG, CR_EXTSTAT_RESET },
};
#endif
#if defined(CONFIG_BVME6000_SCC)
static const struct {
unsigned reg, val;
} bvme_init_tab[] = {
/* Values for BVME6000 */
/* no parity, 1 stop bit, async, 1:16 */
{ AUX1_CTRL_REG, A1CR_PARITY_NONE|A1CR_MODE_ASYNC_1|A1CR_CLKMODE_x16 },
/* parity error is special cond, ints disabled, no DMA */
{ INT_AND_DMA_REG, IDR_PARERR_AS_SPCOND | IDR_RX_INT_DISAB },
/* Rx 8 bits/char, no auto enable, Rx off */
{ RX_CTRL_REG, RCR_CHSIZE_8 },
/* DTR off, Tx 8 bits/char, RTS off, Tx off */
{ TX_CTRL_REG, TCR_CHSIZE_8 },
/* special features off */
{ AUX2_CTRL_REG, 0 },
{ CLK_CTRL_REG, CCR_RTxC_XTAL | CCR_RXCLK_BRG | CCR_TXCLK_BRG },
{ DPLL_CTRL_REG, DCR_BRG_ENAB },
/* Start Rx */
{ RX_CTRL_REG, RCR_RX_ENAB | RCR_CHSIZE_8 },
/* Start Tx */
{ TX_CTRL_REG, TCR_TX_ENAB | TCR_RTS | TCR_DTR | TCR_CHSIZE_8 },
/* Ext/Stat ints: DCD only */
{ INT_CTRL_REG, ICR_ENAB_DCD_INT },
/* Reset Ext/Stat ints */
{ COMMAND_REG, CR_EXTSTAT_RESET },
/* ...again */
{ COMMAND_REG, CR_EXTSTAT_RESET },
};
#endif
if (!(port->gs.flags & ASYNC_INITIALIZED)) {
save_flags(flags);
cli();
#if defined(CONFIG_MVME147_SCC) || defined(CONFIG_MVME162_SCC)
if (MACH_IS_MVME147 || MACH_IS_MVME16x) {
for (i=0; i<sizeof(mvme_init_tab)/sizeof(*mvme_init_tab); ++i)
SCCwrite(mvme_init_tab[i].reg, mvme_init_tab[i].val);
}
#endif
#if defined(CONFIG_BVME6000_SCC)
if (MACH_IS_BVME6000) {
for (i=0; i<sizeof(bvme_init_tab)/sizeof(*bvme_init_tab); ++i)
SCCwrite(bvme_init_tab[i].reg, bvme_init_tab[i].val);
}
#endif
/* remember status register for detection of DCD and CTS changes */
scc_last_status_reg[channel] = SCCread(STATUS_REG);
port->c_dcd = 0; /* Prevent initial 1->0 interrupt */
scc_setsignals (port, 1,1);
restore_flags(flags);
}
tty->driver_data = port;
port->gs.tty = tty;
port->gs.count++;
retval = gs_init_port(&port->gs);
if (retval) {
port->gs.count--;
return retval;
}
port->gs.flags |= GS_ACTIVE;
if (port->gs.count == 1) {
MOD_INC_USE_COUNT;
}
retval = gs_block_til_ready(port, filp);
if (retval) {
MOD_DEC_USE_COUNT;
port->gs.count--;
return retval;
}
if ((port->gs.count == 1) && (port->gs.flags & ASYNC_SPLIT_TERMIOS)) {
if (tty->driver.subtype == SERIAL_TYPE_NORMAL)
*tty->termios = port->gs.normal_termios;
else
*tty->termios = port->gs.callout_termios;
scc_set_real_termios (port);
}
port->gs.session = current->session;
port->gs.pgrp = current->pgrp;
port->c_dcd = scc_get_CD (port);
scc_enable_rx_interrupts(port);
return 0;
}
