void
idt_init(void)
{
extern struct Segdesc gdt[];
// Setup a TSS so that we get the right stack
// when we trap to the kernel.
ts.ts_esp0 = KSTACKTOP;
ts.ts_ss0 = GD_KD;
// Love to put this code in the initialization of gdt,
// but the compiler generates an error incorrectly.
gdt[GD_TSS >> 3] = SEG16(STS_T32A, (u_long) (&ts),
sizeof(struct Taskstate), 0);
gdt[GD_TSS >> 3].sd_s = 0;
printf("????????????????????????\n");
// Load the TSS
ltr(GD_TSS);
idt[0x0] = GATE(STS_IG32, GD_KT, (int)&myint0, 3);
idt[0xE] = GATE(STS_IG32, GD_KT, (int)&myint14, 3);
idt[0x30] = GATE(STS_IG32, GD_KT, (int)&myint30, 3);
printf("????????????????????????%x\n", idt[0x30]);
// Load the IDT
asm volatile("lidt idt_pd+2");
}
// Set up CPU's segment descriptors and task state for a given process.
// If p==0, set up for "idle" state for when scheduler() is running.
void
setupsegs(struct proc *p)
{
struct cpu *c;
pushcli();
c = &cpus[cpu()];
c->ts.ss0 = SEG_KDATA << 3;
if(p)
c->ts.esp0 = (uint)(p->kstack + KSTACKSIZE);
else
c->ts.esp0 = 0xffffffff;
c->gdt[0] = SEG_NULL;
c->gdt[SEG_KCODE] = SEG(STA_X|STA_R, 0, 0x100000 + 64*1024-1, 0);
c->gdt[SEG_KDATA] = SEG(STA_W, 0, 0xffffffff, 0);
c->gdt[SEG_TSS] = SEG16(STS_T32A, (uint)&c->ts, sizeof(c->ts)-1, 0);
c->gdt[SEG_TSS].s = 0;
if(p){
c->gdt[SEG_UCODE] = SEG(STA_X|STA_R, (uint)p->mem, p->sz-1, DPL_USER);
c->gdt[SEG_UDATA] = SEG(STA_W, (uint)p->mem, p->sz-1, DPL_USER);
} else {
c->gdt[SEG_UCODE] = SEG_NULL;
c->gdt[SEG_UDATA] = SEG_NULL;
}
lgdt(c->gdt, sizeof(c->gdt));
ltr(SEG_TSS << 3);
popcli();
}
void
idt_init(void)
{
extern struct Segdesc gdt[];
// LAB 2: Your code here.
//extern char* t_brkpt_lbl;
extern char t_brkpt_lbl[];
SETGATE(idt[3], 0, GD_KT, t_brkpt_lbl, 3);
// Hint: Must this gate be accessible from userlevel?
// LAB 3: Your code here.
// Setup a TSS so that we get the right stack
// when we trap to the kernel.
ts.ts_esp0 = KSTACKTOP;
ts.ts_ss0 = GD_KD;
// Initialize the TSS field of the gdt.
gdt[GD_TSS >> 3] = SEG16(STS_T32A, (uint32_t) (&ts),
sizeof(struct Taskstate), 0);
gdt[GD_TSS >> 3].sd_s = 0;
// Load the TSS
ltr(GD_TSS);
// Load the IDT
asm volatile("lidt idt_pd");
}
void
idt_init(void)
{
extern struct Segdesc gdt[];
// LAB 3: Your code here.
assert(sizeof(struct Gatedesc) == SZ_GATEDESC);
assert(sizeof(struct Pseudodesc) == SZ_PSEUDODESC);
assert(sizeof(struct Trapframe) == SIZEOF_STRUCT_TRAPFRAME);
clog("idt_pd = %u, %p", idt_pd.pd_lim, idt_pd.pd_base);
//print_idt(idt);
setup_idt();
//print_idt(idt);
// Setup a TSS so that we get the right stack
// when we trap to the kernel.
ts.ts_esp0 = KSTACKTOP;
ts.ts_ss0 = GD_KD;
// Initialize the TSS field of the gdt.
gdt[GD_TSS >> 3] = SEG16(STS_T32A, (uint32_t) (&ts),
sizeof(struct Taskstate), 0);
gdt[GD_TSS >> 3].sd_s = 0;
// Load the TSS
ltr(GD_TSS);
// Load the IDT
asm volatile("lidt idt_pd");
}
// Initialize and load the per-CPU TSS and IDT
void
trap_init_percpu(void)
{
// The example code here sets up the Task State Segment (TSS) and
// the TSS descriptor for CPU 0. But it is incorrect if we are
// running on other CPUs because each CPU has its own kernel stack.
// Fix the code so that it works for all CPUs.
//
// Hints:
// - The macro "thiscpu" always refers to the current CPU's
// struct CpuInfo;
// - The ID of the current CPU is given by cpunum() or
// thiscpu->cpu_id;
// - Use "thiscpu->cpu_ts" as the TSS for the current CPU,
// rather than the global "ts" variable;
// - Use gdt[(GD_TSS0 >> 3) + i] for CPU i's TSS descriptor;
// - You mapped the per-CPU kernel stacks in mem_init_mp()
//
// ltr sets a 'busy' flag in the TSS selector, so if you
// accidentally load the same TSS on more than one CPU, you'll
// get a triple fault. If you set up an individual CPU's TSS
// wrong, you may not get a fault until you try to return from
// user space on that CPU.
//
// LAB 4: Your code here:
//------------ Lab4 ----------------------------------------------------------------------------------------
int cpuid = thiscpu->cpu_id;
thiscpu->cpu_ts.ts_esp0 = KSTACKTOP - cpuid * (KSTKGAP + KSTKSIZE);
thiscpu->cpu_ts.ts_ss0 = GD_KD;
gdt[(GD_TSS0 >> 3) + cpuid] = SEG16(STS_T32A, (uint32_t) (&(thiscpu->cpu_ts)),
sizeof(struct Taskstate), 0);
gdt[(GD_TSS0 >> 3) + cpuid].sd_s = 0;
ltr(GD_TSS0 + (cpuid << 3));
lidt(&idt_pd);
//------------ Lab4 ----------------------------------------------------------------------------------------
/*
// Setup a TSS so that we get the right stack
// when we trap to the kernel.
ts.ts_esp0 = KSTACKTOP;
ts.ts_ss0 = GD_KD;
// Initialize the TSS slot of the gdt.
gdt[GD_TSS0 >> 3] = SEG16(STS_T32A, (uint32_t) (&ts),
sizeof(struct Taskstate), 0);
gdt[GD_TSS0 >> 3].sd_s = 0;
// Load the TSS selector (like other segment selectors, the
// bottom three bits are special; we leave them 0)
ltr(GD_TSS0);
// Load the IDT
lidt(&idt_pd);
*/
}
// Switch TSS and h/w page table to correspond to process p.
void switchuvm(struct proc *p) {
pushcli();
cpu->gdt[SEG_TSS] = SEG16(STS_T32A, &cpu->ts, sizeof(cpu->ts)-1, 0);
cpu->gdt[SEG_TSS].s = 0;
cpu->ts.ss0 = SEG_KDATA << 3;
cpu->ts.esp0 = (uint) proc->kstack + KSTACKSIZE;
ltr(SEG_TSS << 3);
if (p->pgdir == 0)
panic("switchuvm: no pgdir");
lcr3(v2p(p->pgdir)); // switch to new address space
popcli();
}
// Set up CPU's segment descriptors and current process task state.
void
usegment(void)
{
pushcli();
cpu->gdt[SEG_UCODE] = SEG(STA_X|STA_R, proc->mem, proc->sz-1, DPL_USER);
cpu->gdt[SEG_UDATA] = SEG(STA_W, proc->mem, proc->sz-1, DPL_USER);
cpu->gdt[SEG_TSS] = SEG16(STS_T32A, &cpu->ts, sizeof(cpu->ts)-1, 0);
cpu->gdt[SEG_TSS].s = 0;
cpu->ts.ss0 = SEG_KDATA << 3;
cpu->ts.esp0 = (uint)proc->kstack + KSTACKSIZE;
ltr(SEG_TSS << 3);
popcli();
}
void
idt_init(void)
{
extern struct Segdesc gdt[];
// LAB 3: Your code here.
SETGATE(idt[T_DIVIDE], 0, GD_KT, divide_error, 0);
SETGATE(idt[T_DEBUG], 0, GD_KT, debug, 0);
SETGATE(idt[T_NMI], 0, GD_KT, nmi, 0);
SETGATE(idt[T_BRKPT], 0, GD_KT, break_point, 3);
SETGATE(idt[T_OFLOW], 0, GD_KT, overflow, 0);
SETGATE(idt[T_BOUND], 0, GD_KT, bounds, 0);
SETGATE(idt[T_ILLOP], 0, GD_KT, invalid_op, 0);
SETGATE(idt[T_DEVICE], 0, GD_KT, device_not_available, 0);
SETGATE(idt[T_DBLFLT], 0, GD_KT, double_fault, 0);
SETGATE(idt[T_TSS], 0, GD_KT, invalid_TSS, 0);
SETGATE(idt[T_SEGNP], 0, GD_KT, segment_not_present, 0);
SETGATE(idt[T_STACK], 0, GD_KT, stack_segment, 0);
SETGATE(idt[T_GPFLT], 0, GD_KT, general_protection, 0);
SETGATE(idt[T_PGFLT], 0, GD_KT, page_fault, 0);
SETGATE(idt[T_FPERR], 0, GD_KT, float_point_error, 0);
SETGATE(idt[T_ALIGN], 0, GD_KT, alignment_check, 0);
SETGATE(idt[T_MCHK], 0, GD_KT, machine_check, 0);
SETGATE(idt[T_SIMDERR], 0, GD_KT, SIMD_float_point_error, 0);
SETGATE(idt[IRQ_OFFSET + IRQ_TIMER], 0, GD_KT, timer, 0);
SETGATE(idt[T_SYSCALL], 0, GD_KT, system_call, 3);
// Setup a TSS so that we get the right stack
// when we trap to the kernel.
ts.ts_esp0 = KSTACKTOP;
ts.ts_ss0 = GD_KD;
// Initialize the TSS field of the gdt.
gdt[GD_TSS >> 3] = SEG16(STS_T32A, (uint32_t) (&ts),
sizeof(struct Taskstate), 0);
gdt[GD_TSS >> 3].sd_s = 0;
// Load the TSS
ltr(GD_TSS);
// Load the IDT
asm volatile("lidt idt_pd");
}
// Initialize and load the per-CPU TSS and IDT
void
trap_init_percpu(void)
{
// Setup a TSS so that we get the right stack
// when we trap to the kernel.
ts.ts_esp0 = KSTACKTOP;
ts.ts_ss0 = GD_KD;
// Initialize the TSS slot of the gdt.
gdt[GD_TSS0 >> 3] = SEG16(STS_T32A, (uint32_t) (&ts),
sizeof(struct Taskstate) - 1, 0);
gdt[GD_TSS0 >> 3].sd_s = 0;
// Load the TSS selector (like other segment selectors, the
// bottom three bits are special; we leave them 0)
ltr(GD_TSS0);
// Load the IDT
lidt(&idt_pd);
}
void
idt_init(void)
{
extern struct Segdesc gdt[];
extern void divide_entry();
extern void debug_entry();
extern void nmi_entry();
extern void brkpt_entry();
extern void oflow_entry();
extern void bound_entry();
extern void illop_entry();
extern void device_entry();
extern void dblflt_entry();
extern void tts_entry();
extern void segnp_entry();
extern void stack_entry();
extern void gpflt_entry();
extern void pgflt_entry();
extern void fperr_entry();
extern void align_entry();
extern void mchk_entry();
extern void simderr_entry();
extern void syscall_entry();
extern void irq_timer_entry();
extern void irq_kbd_entry();
extern void irq_serial_entry();
extern void irq_spurious_entry();
extern void irq_error_entry();
// LAB 3: Your code here.
SETGATE(idt[T_DIVIDE], 0, GD_KT, divide_entry, 0);
SETGATE(idt[T_DEBUG], 0, GD_KT, debug_entry, 0);
SETGATE(idt[T_NMI], 0, GD_KT, nmi_entry, 0);
SETGATE(idt[T_BRKPT], 0, GD_KT, brkpt_entry, 3);
SETGATE(idt[T_OFLOW], 0, GD_KT, oflow_entry, 3);
SETGATE(idt[T_BOUND], 0, GD_KT, bound_entry, 3);
SETGATE(idt[T_ILLOP], 0, GD_KT, illop_entry, 3);
SETGATE(idt[T_DEVICE], 0, GD_KT, device_entry, 3);
SETGATE(idt[T_DBLFLT], 0, GD_KT, dblflt_entry, 3);
SETGATE(idt[T_TSS], 0, GD_KT, tts_entry, 0);
SETGATE(idt[T_STACK], 0, GD_KT, stack_entry, 0);
SETGATE(idt[T_GPFLT], 0, GD_KT, gpflt_entry, 0);
SETGATE(idt[T_PGFLT], 0, GD_KT, pgflt_entry, 3);
SETGATE(idt[T_FPERR], 0, GD_KT, fperr_entry, 0);
SETGATE(idt[T_ALIGN], 0, GD_KT, align_entry, 0);
SETGATE(idt[T_MCHK], 0, GD_KT, mchk_entry, 0);
SETGATE(idt[T_SIMDERR], 0, GD_KT, simderr_entry, 0);
SETGATE(idt[T_SYSCALL],0, GD_KT, syscall_entry, 3);
/* lab4 irqs */
SETGATE(idt[IRQ_OFFSET + IRQ_TIMER], 0, GD_KT, irq_timer_entry, 0);
/* lab4 irqs */
// Setup a TSS so that we get the right stack
// when we trap to the kernel.
ts.ts_esp0 = KSTACKTOP;
ts.ts_ss0 = GD_KD;
// Initialize the TSS field of the gdt.
gdt[GD_TSS >> 3] = SEG16(STS_T32A, (uint32_t) (&ts),
sizeof(struct Taskstate), 0);
gdt[GD_TSS >> 3].sd_s = 0;
// Load the TSS
ltr(GD_TSS);
// Load the IDT
asm volatile("lidt idt_pd");
}
void
idt_init(void)
{
extern struct Segdesc gdt[];
// LAB 2: Your code here.
extern uint32_t handler0;// divide error
extern uint32_t handler1;// debug exception
extern uint32_t handler2;// non-maskable interrupt
extern uint32_t handler3;// breakpoint
extern uint32_t handler4;// overflow
extern uint32_t handler5;// bounds check
extern uint32_t handler6;// illegal opcode
extern uint32_t handler7;// device not available
extern uint32_t handler8;// double fault
extern uint32_t handler9;// reserved (not generated by recent processors)
extern uint32_t handler10;// invalid task switch segment
extern uint32_t handler11;// segment not present
extern uint32_t handler12;// stack exception
extern uint32_t handler13;// general protection fault
extern uint32_t handler14;// page fault
extern uint32_t handler15;// reserved
extern uint32_t handler16;// floating point error
extern uint32_t handler17;// aligment check
extern uint32_t handler18;// machine check
extern uint32_t handler19;// SIMD floating point error
extern uint32_t handler48;// System Call
SETGATE(idt[1],1,GD_KT,&handler1,0);
SETGATE(idt[2],1,GD_KT,&handler2,0);
SETGATE(idt[3],1,GD_KT,&handler3,3);//intercept accessible from userlevel
SETGATE(idt[4],1,GD_KT,&handler4,0);
SETGATE(idt[5],1,GD_KT,&handler5,0);
SETGATE(idt[6],1,GD_KT,&handler6,0);
SETGATE(idt[7],1,GD_KT,&handler7,0);
SETGATE(idt[8],1,GD_KT,&handler8,0);
SETGATE(idt[9],1,GD_KT,&handler9,0);
SETGATE(idt[10],1,GD_KT,&handler10,0);
SETGATE(idt[11],1,GD_KT,&handler11,0);
SETGATE(idt[12],1,GD_KT,&handler12,0);
SETGATE(idt[13],1,GD_KT,&handler13,0);
SETGATE(idt[14],1,GD_KT,&handler14,0);
SETGATE(idt[15],1,GD_KT,&handler15,0);
SETGATE(idt[16],1,GD_KT,&handler16,0);
SETGATE(idt[17],1,GD_KT,&handler17,0);
SETGATE(idt[18],1,GD_KT,&handler18,0);
SETGATE(idt[19],1,GD_KT,&handler19,0);
// Set a gate for the system call interrupt.
// Hint: Must this gate be accessible from userlevel?
// LAB 3: Your code here.
SETGATE(idt[48],0,GD_KT,&handler48,3);
// Setup a TSS so that we get the right stack
// when we trap to the kernel.
ts.ts_esp0 = KSTACKTOP;
ts.ts_ss0 = GD_KD;
// Initialize the TSS field of the gdt.
gdt[GD_TSS >> 3] = SEG16(STS_T32A, (uint32_t) (&ts),
sizeof(struct Taskstate), 0);
gdt[GD_TSS >> 3].sd_s = 0;
// Load the TSS
ltr(GD_TSS);
// Load the IDT
asm volatile("lidt idt_pd");
}
void
idt_init(void)
{
extern struct Segdesc gdt[];
// LAB 3: Your code here.
// trap handler funtions defined in trapentry.S
extern void trap_divide();
extern void trap_debug();
extern void trap_nmi();
extern void trap_brkpt();
extern void trap_oflow();
extern void trap_bound();
extern void trap_illop();
extern void trap_device();
extern void trap_dblflt();
//extern void trap_coproc();
extern void trap_tss();
extern void trap_segnp();
extern void trap_stack();
extern void trap_gpflt();
extern void trap_pgflt();
//extern void trap_res();
extern void trap_fperr();
extern void trap_align();
extern void trap_mchk();
extern void trap_simderr();
extern void trap_syscall();
extern void irq0_handler();
extern void irq1_handler();
extern void irq2_handler();
extern void irq3_handler();
extern void irq4_handler();
extern void irq5_handler();
extern void irq6_handler();
extern void irq7_handler();
extern void irq8_handler();
extern void irq9_handler();
extern void irq10_handler();
extern void irq11_handler();
extern void irq12_handler();
extern void irq13_handler();
extern void irq14_handler();
extern void irq15_handler();
SETGATE(idt[T_DIVIDE], 1, GD_KT, trap_divide, 0);
SETGATE(idt[T_DEBUG], 1, GD_KT, trap_debug, 0);
SETGATE(idt[T_NMI], 0, GD_KT, trap_nmi, 0);
SETGATE(idt[T_BRKPT], 1, GD_KT, trap_brkpt, 3);
SETGATE(idt[T_OFLOW], 1, GD_KT, trap_oflow, 0);
SETGATE(idt[T_BOUND], 1, GD_KT, trap_bound, 0);
SETGATE(idt[T_ILLOP], 1, GD_KT, trap_illop, 0);
SETGATE(idt[T_DEVICE], 1, GD_KT, trap_device, 0);
SETGATE(idt[T_DBLFLT], 1, GD_KT, trap_dblflt, 0);
//SETGATE(idt[T_COPROC], 0, GD_KT, trap_coproc, 0);
SETGATE(idt[T_TSS], 1, GD_KT, trap_tss, 0);
SETGATE(idt[T_SEGNP], 1, GD_KT, trap_segnp, 0);
SETGATE(idt[T_STACK], 1, GD_KT, trap_stack, 0);
SETGATE(idt[T_GPFLT], 1, GD_KT, trap_gpflt, 0);
SETGATE(idt[T_PGFLT], 1, GD_KT, trap_pgflt, 0);
//SETGATE(idt[T_RES], 0, GD_KT, trap_res, 0);
SETGATE(idt[T_FPERR], 1, GD_KT, trap_fperr, 0);
SETGATE(idt[T_ALIGN], 1, GD_KT, trap_align, 0);
SETGATE(idt[T_MCHK], 1, GD_KT, trap_mchk, 0);
SETGATE(idt[T_SIMDERR], 1, GD_KT, trap_simderr, 0);
//Initial system call entry
SETGATE(idt[T_SYSCALL], 1, GD_KT, trap_syscall, 3);
//Initial IRQ handlers
SETGATE(idt[IRQ_OFFSET], 0, GD_KT, irq0_handler, 0);
SETGATE(idt[IRQ_OFFSET + 1], 0, GD_KT, irq1_handler, 0);
SETGATE(idt[IRQ_OFFSET + 2], 0, GD_KT, irq2_handler, 0);
SETGATE(idt[IRQ_OFFSET + 3], 0, GD_KT, irq3_handler, 0);
SETGATE(idt[IRQ_OFFSET + 4], 0, GD_KT, irq4_handler, 0);
SETGATE(idt[IRQ_OFFSET + 5], 0, GD_KT, irq5_handler, 0);
SETGATE(idt[IRQ_OFFSET + 6], 0, GD_KT, irq6_handler, 0);
SETGATE(idt[IRQ_OFFSET + 7], 0, GD_KT, irq7_handler, 0);
SETGATE(idt[IRQ_OFFSET + 8], 0, GD_KT, irq8_handler, 0);
SETGATE(idt[IRQ_OFFSET + 9], 0, GD_KT, irq9_handler, 0);
SETGATE(idt[IRQ_OFFSET + 10], 0, GD_KT, irq10_handler, 0);
SETGATE(idt[IRQ_OFFSET + 11], 0, GD_KT, irq11_handler, 0);
SETGATE(idt[IRQ_OFFSET + 12], 0, GD_KT, irq12_handler, 0);
SETGATE(idt[IRQ_OFFSET + 13], 0, GD_KT, irq13_handler, 0);
SETGATE(idt[IRQ_OFFSET + 14], 0, GD_KT, irq14_handler, 0);
SETGATE(idt[IRQ_OFFSET + 15], 0, GD_KT, irq15_handler, 0);
// Setup a TSS so that we get the right stack
// when we trap to the kernel.
ts.ts_esp0 = KSTACKTOP;
ts.ts_ss0 = GD_KD;
// Initialize the TSS field of the gdt.
gdt[GD_TSS >> 3] = SEG16(STS_T32A, (uint32_t) (&ts),
sizeof(struct Taskstate), 0);
gdt[GD_TSS >> 3].sd_s = 0;
// Load the TSS
ltr(GD_TSS);
// Load the IDT
asm volatile("lidt idt_pd");
}
void
idt_init(void)
{
extern struct Segdesc gdt[];
// LAB 3: Your code here.
// Exceptions and traps
SETGATE(idt[T_DIVIDE], 0, GD_KT, trap_divide, 0);
SETGATE(idt[T_DEBUG], 0, GD_KT, trap_debug, 3);
SETGATE(idt[T_NMI], 0, GD_KT, trap_nmi, 0);
SETGATE(idt[T_BRKPT], 0, GD_KT, trap_brkpt, 3);
SETGATE(idt[T_OFLOW], 0, GD_KT, trap_oflow, 0);
SETGATE(idt[T_BOUND], 0, GD_KT, trap_bound, 0);
SETGATE(idt[T_ILLOP], 0, GD_KT, trap_illop, 0);
SETGATE(idt[T_DEVICE], 0, GD_KT, trap_device, 0);
SETGATE(idt[T_DBLFLT], 0, GD_KT, trap_dblflt, 0);
SETGATE(idt[T_TSS], 0, GD_KT, trap_tss, 0);
SETGATE(idt[T_SEGNP], 0, GD_KT, trap_segnp, 0);
SETGATE(idt[T_STACK], 0, GD_KT, trap_stack, 0);
SETGATE(idt[T_GPFLT], 0, GD_KT, trap_gpflt, 0);
SETGATE(idt[T_PGFLT], 0, GD_KT, trap_pgflt, 0);
SETGATE(idt[T_FPERR], 0, GD_KT, trap_fperr, 0);
SETGATE(idt[T_ALIGN], 0, GD_KT, trap_align, 0);
SETGATE(idt[T_MCHK], 0, GD_KT, trap_mchk, 0);
SETGATE(idt[T_SIMDERR], 0, GD_KT, trap_simderr, 0);
// External interrupts
SETGATE(idt[IRQ_OFFSET + 0x0], 0, GD_KT, trap_irq_0, 0);
SETGATE(idt[IRQ_OFFSET + 0x1], 0, GD_KT, trap_irq_1, 0);
SETGATE(idt[IRQ_OFFSET + 0x2], 0, GD_KT, trap_irq_2, 0);
SETGATE(idt[IRQ_OFFSET + 0x3], 0, GD_KT, trap_irq_3, 0);
SETGATE(idt[IRQ_OFFSET + 0x4], 0, GD_KT, trap_irq_4, 0);
SETGATE(idt[IRQ_OFFSET + 0x5], 0, GD_KT, trap_irq_5, 0);
SETGATE(idt[IRQ_OFFSET + 0x6], 0, GD_KT, trap_irq_6, 0);
SETGATE(idt[IRQ_OFFSET + 0x7], 0, GD_KT, trap_irq_7, 0);
SETGATE(idt[IRQ_OFFSET + 0x8], 0, GD_KT, trap_irq_8, 0);
SETGATE(idt[IRQ_OFFSET + 0x9], 0, GD_KT, trap_irq_9, 0);
SETGATE(idt[IRQ_OFFSET + 0xa], 0, GD_KT, trap_irq_a, 0);
SETGATE(idt[IRQ_OFFSET + 0xb], 0, GD_KT, trap_irq_b, 0);
SETGATE(idt[IRQ_OFFSET + 0xc], 0, GD_KT, trap_irq_c, 0);
SETGATE(idt[IRQ_OFFSET + 0xd], 0, GD_KT, trap_irq_d, 0);
SETGATE(idt[IRQ_OFFSET + 0xe], 0, GD_KT, trap_irq_e, 0);
SETGATE(idt[IRQ_OFFSET + 0xf], 0, GD_KT, trap_irq_f, 0);
// syscall should be trap,
// SETCALLGATE(idt[T_SYSCALL], GD_KT, trap_syscall, 0);
SETGATE(idt[T_SYSCALL], 0, GD_KT, trap_syscall, 3);
// Setup a TSS so that we get the right stack
// when we trap to the kernel.
ts.ts_esp0 = KSTACKTOP;
ts.ts_ss0 = GD_KD;
// Initialize the TSS field of the gdt.
gdt[GD_TSS >> 3] = SEG16(STS_T32A, (uint32_t) (&ts),
sizeof(struct Taskstate), 0);
gdt[GD_TSS >> 3].sd_s = 0;
// Load the TSS
ltr(GD_TSS);
// Load the IDT
asm volatile("lidt idt_pd");
}
