static SEM_PC
SEM_FN_NAME (lm32bf,calli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_bi.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
{
SI opval = ADDSI (pc, 4);
CPU (h_gr[((UINT) 29)]) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
{
USI opval = EXTSISI (FLD (i_call));
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
SEM_BRANCH_FINI (vpc);
return vpc;
#undef FLD
}
static SEM_PC
SEM_FN_NAME (lm32bf,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_empty.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{
#if WITH_SCACHE_PBB_LM32BF
#if defined DEFINE_SWITCH || defined FAST_P
/* In the switch case FAST_P is a constant, allowing several optimizations
in any called inline functions. */
vpc = lm32bf_pbb_begin (current_cpu, FAST_P);
#else
#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
vpc = lm32bf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
#else
vpc = lm32bf_pbb_begin (current_cpu, 0);
#endif
#endif
#endif
}
return vpc;
#undef FLD
}
static SEM_PC
SEM_FN_NAME (lm32bf,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_empty.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{
#if WITH_SCACHE_PBB_LM32BF
#ifdef DEFINE_SWITCH
vpc = lm32bf_pbb_cti_chain (current_cpu, sem_arg,
pbb_br_type, pbb_br_npc);
BREAK (sem);
#else
/* FIXME: Allow provision of explicit ifmt spec in insn spec. */
vpc = lm32bf_pbb_cti_chain (current_cpu, sem_arg,
CPU_PBB_BR_TYPE (current_cpu),
CPU_PBB_BR_NPC (current_cpu));
#endif
#endif
}
return vpc;
#undef FLD
}
static SEM_PC
SEM_FN_NAME (lm32bf,wcsr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_wcsr.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
lm32bf_wcsr_insn (current_cpu, FLD (f_csr), CPU (h_gr[FLD (f_r1)]));
return vpc;
#undef FLD
}
static int
model_lm32_break (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
cycles += lm32bf_model_lm32_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static SEM_PC
SEM_FN_NAME (lm32bf,muli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_addi.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI opval = MULSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm))));
CPU (h_gr[FLD (f_r1)]) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
return vpc;
#undef FLD
}
static SEM_PC
SEM_FN_NAME (lm32bf,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_empty.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{
#if WITH_SCACHE_PBB_LM32BF
lm32bf_pbb_before (current_cpu, sem_arg);
#endif
}
return vpc;
#undef FLD
}
static SEM_PC
SEM_FN_NAME (lm32bf,cmpgeu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_user.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
SI opval = GEUSI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]));
CPU (h_gr[FLD (f_r2)]) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
return vpc;
#undef FLD
}
static SEM_PC
SEM_FN_NAME (lm32bf,modu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_user.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
USI opval = lm32bf_modu_insn (current_cpu, pc, FLD (f_r0), FLD (f_r1), FLD (f_r2));
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
SEM_BRANCH_FINI (vpc);
return vpc;
#undef FLD
}
static SEM_PC
SEM_FN_NAME (lm32bf,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_be.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (NESI (CPU (h_gr[FLD (f_r0)]), CPU (h_gr[FLD (f_r1)]))) {
{
USI opval = FLD (i_branch);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
abuf->written = written;
SEM_BRANCH_FINI (vpc);
return vpc;
#undef FLD
}
static SEM_PC
SEM_FN_NAME (lm32bf,x_invalid) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_empty.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{
/* Update the recorded pc in the cpu state struct.
Only necessary for WITH_SCACHE case, but to avoid the
conditional compilation .... */
SET_H_PC (pc);
/* Virtual insns have zero size. Overwrite vpc with address of next insn
using the default-insn-bitsize spec. When executing insns in parallel
we may want to queue the fault and continue execution. */
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
}
return vpc;
#undef FLD
}
SI opval = INVSI (XORSI (CPU (h_gr[FLD (f_r0)]), ZEXTSISI (FLD (f_uimm))));
CPU (h_gr[FLD (f_r1)]) = opval;
TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
}
return vpc;
#undef FLD
}
/* break: break */
static SEM_PC
SEM_FN_NAME (lm32bf,break) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_empty.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_BRANCH_INIT
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
USI opval = lm32bf_break_insn (current_cpu, pc);
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
SEM_BRANCH_FINI (vpc);
return vpc;
#undef FLD
}
