/* Does not destroy a and b. */
void sc_div(mscalar a, mscalar b, mscalar c)
{
unsigned long TT[4];
unsigned long SSS[4];
int e;
e = VAL4(b);
SET4(TT, b);
SET4(SSS, a);
while (e >= 64) {
TT[0] = TT[1];
TT[1] = TT[2];
TT[2] = TT[3];
TT[3] = 0;
SSS[0] = SSS[1];
SSS[1] = SSS[2];
SSS[2] = SSS[3];
SSS[3] = 0;
e = e - 64;
}
DIV4(TT, e);
DIV4(SSS, e);
INV4(TT);
MUL4(c, SSS, TT);
}
go_self(char const *tmpname, char *argv[], char *envp[])
{
// Old FreeBSD does not have /proc/self, so use /proc/<pid> instead.
// Open the temp file.
int const fdi = open(tmpname, O_RDONLY, 0);
if (0 <= fdi) {
// 17 chars for "/proc/PPPPP/fd/XX" should be enough, but we
// play safe in case there will be 32-bit pid_t at some time.
//char procself_buf[17+1];
char procself_buf[31+1];
// Compute name of temp fdi.
SET4(procself_buf + 0, '/', 'p', 'r', 'o');
SET4(procself_buf + 4, 'c', '/', 0 , 0 );
{
char *const procself = upx_itoa(getpid(), procself_buf + 6);
SET4(procself, '/', 'f', 'd', '/');
upx_itoa(fdi, procself + 4);
}
// Check for working /proc/self/fd/X by accessing the
// temp file again, now via temp fdi.
if (UPX2 == (unsigned) access(procself_buf, R_OK | X_OK)) {
// Now it's safe to unlink the temp file (as it is still open).
unlink(tmpname);
// Set the file close-on-exec.
fcntl(fdi, F_SETFD, FD_CLOEXEC);
// Execute the original program via /proc/self/fd/X.
execve(procself_buf, argv, envp);
// NOTE: if we get here we've lost.
// 2008-March: Ubuntu 7.10 linux-image-2.6.22-14.52-generic
// and SuSE 10.3 have a patch to fs/dcache.c which causes
// execve() [above] to fail with ENOENT.
// Fedora kernel-2.6.22.14-72.fc6 omits the patch, and works:
// https://sourceforge.net/tracker/?func=detail&atid=102331&aid=1825006&group_id=2331
// Now we must re-create the file; it was unlink()ed!
// link(procself_buf, tmpname) gets EXDEV (cross-device link).
// Luckily we still have an open fdi to the file.
// Errors from {lseek, mmap, open, write} are all caught
// by the one check on write().
unsigned const lenf = lseek(fdi, 0, SEEK_END);
char *const buf = mmap((char *)0, lenf, PROT_READ|PROT_WRITE,
MAP_PRIVATE, fdi, 0);
int const fdo = open(tmpname, O_WRONLY | O_CREAT | O_EXCL, 0700);
if (lenf!=(unsigned)write(fdo, buf, lenf)) {
exit(127);
}
close(fdo);
}
// The proc filesystem isn't working. No problem.
close(fdi);
}
return fdi;
}
int Encrypt_Xor(unsigned char *out, unsigned char *in, u64 nonce[], u256 rk[], u64 key[], int numbytes)
{
u64 x[2],y[2];
u256 X[5],Y[5];
if (numbytes==16){
x[0]=nonce[1]; y[0]=nonce[0]; nonce[0]++;
Enc(x,y,key,1);
((u64 *)out)[1]=x[0]; ((u64 *)out)[0]=y[0];
return 0;
}
if (numbytes==32){
x[0]=nonce[1]; y[0]=nonce[0]; nonce[0]++;
x[1]=nonce[1]; y[1]=nonce[0]; nonce[0]++;
Enc(x,y,key,2);
((u64 *)out)[1]=x[0]^((u64 *)in)[1]; ((u64 *)out)[0]=y[0]^((u64 *)in)[0];
((u64 *)out)[3]=x[1]^((u64 *)in)[3]; ((u64 *)out)[2]=y[1]^((u64 *)in)[2];
return 0;
}
SET1(X[0],nonce[1]);
SET4(Y[0],nonce[0]);
if (numbytes==64) Enc(X,Y,rk,4);
else{
X[1]=X[0];
SET4(Y[1],nonce[0]);
if (numbytes==128) Enc(X,Y,rk,8);
else{
X[2]=X[0];
SET4(Y[2],nonce[0]);
if (numbytes==192) Enc(X,Y,rk,12);
else{
X[3]=X[0];
SET4(Y[3],nonce[0]);
if (numbytes==256) Enc(X,Y,rk,16);
else{
X[4]=X[0];
SET4(Y[4],nonce[0]);
Enc(X,Y,rk,20);
}
}
}
}
XOR_STORE(in,out,X[0],Y[0]);
if (numbytes>=128) XOR_STORE(in+64,out+64,X[1],Y[1]);
if (numbytes>=192) XOR_STORE(in+128,out+128,X[2],Y[2]);
if (numbytes>=256) XOR_STORE(in+192,out+192,X[3],Y[3]);
if (numbytes>=320) XOR_STORE(in+256,out+256,X[4],Y[4]);
return 0;
}
static void start_dma_transfer(td243fc_rev2_softc_t *sc, jint_t ep_n,
juint32_t size)
{
td243fc_rev2_ep_t *ep = &sc->ep[ep_n];
jbool_t is_in = EP_IS_IN(ep_n);
juint32_t xybuf_size = ep->buf_size;
WRITE4(TD243FC_DMA_EP_SYSTEM_MEM_ADDR_REG((jint_t)(ep_n / 2), is_in),
ep->req ? (juint32_t)ep->req->buffer.dma_addr :
(juint32_t)sc->dma_buf.dma_addr);
if (ep->req)
xybuf_size = MIN(xybuf_size, ep->req->buffer.buffer_size);
else
xybuf_size = MIN(xybuf_size, sc->dma_buf.buffer_size);
TOGGLE_IF_SET(TD243FC_XFILLED_STATUS_REG, TD243FC_EP_BIT_INDEX(ep_n));
TOGGLE_IF_SET(TD243FC_YFILLED_STATUS_REG, TD243FC_EP_BIT_INDEX(ep_n));
TOGGLE_IF_SET(TD243FC_XBUF_INT_STATUS_REG, TD243FC_EP_BIT_INDEX(ep_n));
TOGGLE_IF_SET(TD243FC_YBUF_INT_STATUS_REG, TD243FC_EP_BIT_INDEX(ep_n));
WRITE4(TD243FC_EPN_PACKET_CONTROL_REG((jint_t)(ep_n / 2), is_in),
BFSET4(TD243FC_BUFFERSIZE, xybuf_size - 1) |
BFSET4(TD243FC_TTLBTECNT, size));
SET4(TD243FC_DMA_EP_ENABLE_REG, TD243FC_EP_BIT_INDEX(ep_n));
if (sc->add_to_list)
sc->ep_ready |= TD243FC_EP_BIT_INDEX(ep_n);
else
WRITE4(TD243FC_EP_READY_REG, TD243FC_EP_BIT_INDEX(ep_n));
}
/* Flag: 0/1-Clear/Set */
static jresult_t dcd_stall_ep(jdevice_t dev, pipe_desc_t *pipe, jbool_t flag)
{
td243fc_rev2_softc_t *sc = (td243fc_rev2_softc_t *)j_device_get_softc(dev);
DBG_V(DSLAVE_DCD, ("DCD: dcd_stall_ep, addr=%02x\n", pipe?pipe->address:0));
if (pipe)
{
jint_t ep_n = (jint_t)(pipe->dcd_handle);
jbool_t is_in = EP_IS_IN(ep_n);
ep_n /= 2;
KASSERT(pipe->dcd_handle, ("Pipe was not allocated\n"));
if (flag)
{
SET4(TD243FC_EPN_CONFIG_CONTROL_REG(ep_n, is_in), TD243FC_STL);
pipe->status = PIPE_STALLLED;
}
else
{
TOGGLE_IF_SET(TD243FC_EP_TOGGLE_REG, TD243FC_EP_BIT(ep_n, is_in));
if (pipe->status == PIPE_STALLLED)
{
CLEAR4(TD243FC_EPN_CONFIG_CONTROL_REG(ep_n, is_in),
TD243FC_STL);
pipe->status = PIPE_ENABLED;
start_next_transfer(sc, (jint_t)(pipe->dcd_handle));
}
}
}
else
{
if (flag)
SET4(TD243FC_EPN_CONFIG_CONTROL_REG(0, 1), TD243FC_STL);
else
CLEAR4(TD243FC_EPN_CONFIG_CONTROL_REG(0, 1), TD243FC_STL);
}
return 0;
}
go_self(char const *tmpname, char *argv[], char *envp[])
{
// Old FreeBSD does not have /proc/self, so use /proc/<pid> instead.
// Open the temp file.
int const fdi = open(tmpname, O_RDONLY, 0);
if (0 <= fdi) {
// 17 chars for "/proc/PPPPP/fd/XX" should be enough, but we
// play safe in case there will be 32-bit pid_t at some time.
//char procself_buf[17+1];
char procself_buf[31+1];
// Compute name of temp fdi.
SET4(procself_buf + 0, '/', 'p', 'r', 'o');
SET4(procself_buf + 4, 'c', '/', 0 , 0 );
{
char *const procself = upx_itoa(getpid(), procself_buf + 6);
SET4(procself, '/', 'f', 'd', '/');
upx_itoa(fdi, procself + 4);
}
// Check for working /proc/self/fd/X by accessing the
// temp file again, now via temp fdi.
if (UPX2 == (unsigned) access(procself_buf, R_OK | X_OK)) {
// Now it's safe to unlink the temp file (as it is still open).
unlink(tmpname);
// Set the file close-on-exec.
fcntl(fdi, F_SETFD, FD_CLOEXEC);
// Execute the original program via /proc/self/fd/X.
execve(procself_buf, (char const *const *)argv, (char const *const *)envp);
// NOTE: if we get here we've lost.
}
// The proc filesystem isn't working. No problem.
close(fdi);
}
return fdi;
}
static dcd_hw_init(td243fc_rev2_softc_t *sc)
{
WRITE4(TD243FC_RESET_CONTROL_REG,
TD243FC_RESET_FUNCTION_SIE | TD243FC_RESET_FUNCTION_CONTROLLER);
/* force USB core work as device bit1:0 = 10b, and XCVR mode
* bit 7:6 = 11b */
WRITE4(TD243FC_HARDWARE_MODE_REG, BFSET4(TD243FC_HF, TD243FC_DEVICE) |
BFSET4(TD243FC_OTGXCVR, TD243FC_SE_SE) |
BFSET4(TD243FC_HOSTXCVR, TD243FC_SE_SE));
/* Enable function controller clock */
SET4(TD243FC_CLOCK_CONTROL_REG, TD243FC_FCCLK);
}
extern void
odRedrawAll(void) /* mark all samples for redraw */
{
register int i;
if ((needmapping&(NEWMAP|NEWRGB)) == (NEWMAP|NEWRGB))
return; /* will be called later, anyway */
for (i = odS.nsamp; i--; )
if (odS.ip[i][0] >= 0)
SET4(odS.redraw, i);
/* not right, but not important */
for (i = 0; i < odNViews; i++)
odView[i].n2redraw = odView[i].snext - odView[i].sfirst;
}
static int
imx_gpt_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
{
struct imx_gpt_softc *sc;
uint32_t ticks;
sc = (struct imx_gpt_softc *)et->et_priv;
if (period != 0) {
sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32;
/* Set expected value */
WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + sc->sc_period);
/* Enable compare register 2 Interrupt */
SET4(sc, IMX_GPT_IR, GPT_IR_OF2);
} else if (first != 0) {
extern void
odRedraw( /* redraw view region */
int vn,
int hmin,
int vmin,
int hmax,
int vmax
)
{
int i, j;
register struct ODblock *bp;
register int k;
if ((vn<0) | (vn>=odNViews))
return;
/* check view limits */
if (hmin < 0) hmin = 0;
if (hmax >= odView[vn].hhi) hmax = odView[vn].hhi-1;
if (vmin < 0) vmin = 0;
if (vmax >= odView[vn].vhi) vmax = odView[vn].vhi-1;
if ((hmax <= hmin) | (vmax <= vmin))
return;
/* convert to low resolution */
hmin = hmin * odView[vn].hlow / odView[vn].hhi;
hmax = hmax * odView[vn].hlow / odView[vn].hhi;
vmin = vmin * odView[vn].vlow / odView[vn].vhi;
vmax = vmax * odView[vn].vlow / odView[vn].vhi;
/* mark block samples for redraw, inclusive */
for (i = hmin; i <= hmax; i++)
for (j = vmin; j <= vmax; j++) {
bp = odView[vn].bmap + j*odView[vn].hlow + i;
for (k = bp->nsamp; k--; )
if (odS.ip[bp->first+k][0] >= 0) {
SET4(odS.redraw, bp->first+k);
odView[vn].n2redraw++;
}
}
}
static int
imx_gpt_attach(device_t dev)
{
struct imx_gpt_softc *sc;
int err;
sc = device_get_softc(dev);
if (bus_alloc_resources(dev, imx_gpt_spec, sc->res)) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
sc->sc_dev = dev;
sc->sc_clksrc = GPT_CR_CLKSRC_IPG;
sc->sc_iot = rman_get_bustag(sc->res[0]);
sc->sc_ioh = rman_get_bushandle(sc->res[0]);
switch (sc->sc_clksrc) {
case GPT_CR_CLKSRC_NONE:
device_printf(dev, "can't run timer without clock source\n");
return (EINVAL);
case GPT_CR_CLKSRC_EXT:
device_printf(dev, "Not implemented. Geve me the way to get "
"external clock source frequency\n");
return (EINVAL);
case GPT_CR_CLKSRC_32K:
sc->clkfreq = 32768;
break;
case GPT_CR_CLKSRC_IPG_HIGH:
sc->clkfreq = imx51_get_clock(IMX51CLK_IPG_CLK_ROOT) * 2;
break;
default:
sc->clkfreq = imx51_get_clock(IMX51CLK_IPG_CLK_ROOT);
}
device_printf(dev, "Run on %dKHz clock.\n", sc->clkfreq / 1000);
/* Reset */
WRITE4(sc, IMX_GPT_CR, GPT_CR_SWR);
/* Enable and setup counters */
WRITE4(sc, IMX_GPT_CR,
GPT_CR_CLKSRC_IPG | /* Use IPG clock */
GPT_CR_FRR | /* Just count (FreeRunner mode) */
GPT_CR_STOPEN | /* Run in STOP mode */
GPT_CR_WAITEN | /* Run in WAIT mode */
GPT_CR_DBGEN); /* Run in DEBUG mode */
/* Disable interrupts */
WRITE4(sc, IMX_GPT_IR, 0);
/* Tick every 10us */
/* XXX: must be calculated from clock source frequency */
WRITE4(sc, IMX_GPT_PR, 665);
/* Use 100 KHz */
sc->clkfreq = 100000;
/* Setup and enable the timer interrupt */
err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, imx_gpt_intr,
NULL, sc, &sc->sc_ih);
if (err != 0) {
bus_release_resources(dev, imx_gpt_spec, sc->res);
device_printf(dev, "Unable to setup the clock irq handler, "
"err = %d\n", err);
return (ENXIO);
}
sc->et.et_name = "i.MXxxx GPT Eventtimer";
sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC;
sc->et.et_quality = 1000;
sc->et.et_frequency = sc->clkfreq;
sc->et.et_min_period = (MIN_PERIOD << 32) / sc->et.et_frequency;
sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
sc->et.et_start = imx_gpt_timer_start;
sc->et.et_stop = imx_gpt_timer_stop;
sc->et.et_priv = sc;
et_register(&sc->et);
/* Disable interrupts */
WRITE4(sc, IMX_GPT_IR, 0);
/* ACK any panding interrupts */
WRITE4(sc, IMX_GPT_SR, (GPT_IR_ROV << 1) - 1);
if (device_get_unit(dev) == 0)
imx_gpt_sc = sc;
imx_gpt_timecounter.tc_frequency = sc->clkfreq;
tc_init(&imx_gpt_timecounter);
printf("clock: hz=%d stathz = %d\n", hz, stathz);
device_printf(sc->sc_dev, "timer clock frequency %d\n", sc->clkfreq);
imx_gpt_delay_count = imx51_get_clock(IMX51CLK_ARM_ROOT) / 4000000;
SET4(sc, IMX_GPT_CR, GPT_CR_EN);
return (0);
}
extern void
odDepthMap( /* assign depth map for view */
int vn,
GLfloat *dm
)
{
double d0, d1;
int i, j, hmin, hmax, vmin, vmax;
register int k, l;
if (dm == NULL) { /* free edge map */
if ((vn<0) | (vn>=odNViews))
return; /* too late -- they're gone! */
if (odView[vn].emap != NULL)
free((void *)odView[vn].emap);
odView[vn].emap = NULL;
odView[vn].dmap = NULL;
return;
}
DCHECK(vn<0 | vn>=odNViews, CONSISTENCY,
"bad view number in odDepthMap");
odView[vn].dmap = dm; /* initialize edge map */
if (odView[vn].emap == NULL) {
odView[vn].emap = (int32 *)malloc(
FL4NELS(odView[vn].hlow*odView[vn].vlow)*sizeof(int32));
if (odView[vn].emap == NULL)
error(SYSTEM, "out of memory in odDepthMap");
}
CLR4ALL(odView[vn].emap, odView[vn].hlow*odView[vn].vlow);
/* compute edge map */
vmin = odView[vn].vhi; /* enter loopsville */
for (j = odView[vn].vlow; j--; ) {
vmax = vmin;
vmin = j*odView[vn].vhi/odView[vn].vlow;
hmin = odView[vn].hhi;
for (i = odView[vn].hlow; i--; ) {
hmax = hmin;
hmin = i*odView[vn].hhi/odView[vn].hlow;
for (l = vmin; l < vmax; l++) { /* vertical edges */
d1 = dm[l*odView[vn].hhi+hmin];
for (k = hmin+1; k < hmax; k++) {
d0 = d1;
d1 = dm[l*odView[vn].hhi+k];
if (d0 > (1.+DEPTHEPS)*d1 ||
(1.+DEPTHEPS)*d0 < d1) {
SET4(odView[vn].emap,
j*odView[vn].hlow + i);
break;
}
}
if (k < hmax)
break;
}
if (l < vmax)
continue;
for (k = hmin; k < hmax; k++) { /* horizontal edges */
d1 = dm[vmin*odView[vn].hhi+k];
for (l = vmin+1; l < vmax; l++) {
d0 = d1;
d1 = dm[l*odView[vn].hhi+k];
if (d0 > (1.+DEPTHEPS)*d1 ||
(1.+DEPTHEPS)*d0 < d1) {
SET4(odView[vn].emap,
j*odView[vn].hlow + i);
break;
}
}
if (l < vmax)
break;
}
}
}
}
extern void
odSample( /* add a sample value */
COLR c,
FVECT d,
FVECT p
)
{
FVECT disp;
double d0, d1, h, v, prox;
register VIEW *vw;
int hh, vh;
int res[2];
register int i, id;
DCHECK(odS.nsamp<=0, CONSISTENCY, "no samples allocated in odSample");
/* add value to each view */
for (i = 0; (vw = dev_auxview(i, res)) != NULL; i++) {
DCHECK(i>=odNViews, CONSISTENCY, "too many views in odSample");
CHECK(vw->type!=VT_PER, INTERNAL,
"cannot handle non-perspective views");
if (p != NULL) { /* compute view position */
VSUB(disp, p, vw->vp);
d0 = DOT(disp, vw->vdir);
if (d0 <= vw->vfore+FTINY)
continue; /* too close */
} else {
VCOPY(disp, d);
d0 = DOT(disp, vw->vdir);
if (d0 <= FTINY) /* behind view */
continue;
}
h = DOT(disp,vw->hvec)/(d0*vw->hn2) + 0.5 - vw->hoff;
if (h < 0. || h >= 1.)
continue; /* left or right */
v = DOT(disp,vw->vvec)/(d0*vw->vn2) + 0.5 - vw->voff;
if (v < 0. || v >= 1.)
continue; /* above or below */
hh = h * res[0];
vh = v * res[1];
if (odView[i].dmap != NULL) { /* check depth */
d1 = odView[i].dmap[vh*res[0] + hh];
if (d1 < 0.99*FHUGE && (d0 > (1.+DEPTHEPS)*d1 ||
(1.+DEPTHEPS)*d0 < d1))
continue; /* occlusion error */
}
if (p != NULL) { /* compute closeness (sin^2) */
d1 = DOT(disp, d);
prox = 1. - d1*d1/DOT(disp,disp);
} else
prox = 0.;
/* allocate sample */
id = odAllocBlockSamp(i, hh, vh, prox);
if (id < 0)
continue; /* not good enough */
/* convert color */
tmCvColrs(tmGlobal, &odS.brt[id], odS.chr[id], (COLR *)c, 1);
if (imm_mode | needmapping) /* if immediate mode */
needmapping |= NEWRGB; /* map it later */
else /* else map it now */
tmMapPixels(tmGlobal, odS.rgb[id], &odS.brt[id],
odS.chr[id], 1);
SET4(odS.redraw, id); /* mark for redraw */
odView[i].n2redraw++;
}
}
int
odAllocBlockSamp( /* allocate sample from block */
int vn,
int hh,
int vh,
double prox
)
{
int si[SAMPSPERBLOCK+SAMPSPERBLOCK/4];
int hl, vl;
VIEW *vw;
int res[2];
register struct ODblock *bp;
register int i, j;
/* get block */
hl = hh*odView[vn].hlow/odView[vn].hhi;
vl = vh*odView[vn].vlow/odView[vn].vhi;
bp = odView[vn].bmap + vl*odView[vn].hlow + hl;
if (prox > bp->pthresh)
return(-1); /* worse than free list occupants */
/* check for duplicate pixel */
if (CHK4(odView[vn].pmap, vh*odView[vn].hhi + hh))
i = bp->first + bp->nsamp;
else
i = 0;
while (i-- > bp->first)
if (hh == odS.ip[i][0] && vh == odS.ip[i][1]) { /* found it! */
/* search free list for it */
if (i == bp->free)
break; /* special case */
if (bp->free != ENDFREE)
for (j = bp->free; odS.nextfree(j) != ENDFREE;
j = odS.nextfree(j))
if (odS.nextfree(j) == i) {
odS.nextfree(j) =
odS.nextfree(i);
bp->nused++;
goto gotit;
}
if (prox >= 0.99*odS.closeness(i))
return(-1); /* previous sample is fine */
goto gotit;
}
if (bp->free != ENDFREE) { /* allocate from free list */
i = bp->free;
if ((odS.ip[i][0] >= 0) & (odS.ip[i][1] >= 0))
CLR4(odView[vn].pmap, odS.ip[i][1]*odView[vn].hhi +
odS.ip[i][0]);
bp->free = odS.nextfree(i);
bp->nused++;
goto gotit;
}
DCHECK(bp->nsamp<=0, CONSISTENCY,
"no available samples in odAllocBlockSamp");
DCHECK(bp->nsamp > sizeof(si)/sizeof(si[0]), CONSISTENCY,
"too many samples in odAllocBlockSamp");
/* free some samples */
if ((vw = dev_auxview(vn, res)) == NULL)
error(CONSISTENCY, "bad view number in odAllocBlockSamp");
for (i = bp->nsamp; i--; ) /* figure out which are worse */
si[i] = bp->first + i;
qsort((char *)si, bp->nsamp, sizeof(int), sampcmp);
i = bp->nsamp*SFREEFRAC + .5; /* put them into free list */
if (i >= bp->nsamp) i = bp->nsamp-1; /* paranoia */
bp->pthresh = odS.closeness(si[i]); /* new proximity threshold */
while (--i > 0) {
odS.nextfree(si[i]) = bp->free;
bp->free = si[i];
bp->nused--;
}
i = si[0]; /* use worst sample */
CLR4(odView[vn].pmap, odS.ip[i][1]*odView[vn].hhi + odS.ip[i][0]);
gotit:
odS.ip[i][0] = hh;
odS.ip[i][1] = vh;
odS.closeness(i) = prox;
SET4(odView[vn].pmap, vh*odView[vn].hhi + hh);
return(i);
}
void
check_various (void)
{
mpz_t x, y;
mpz_init (x);
mpz_init (y);
mpz_realloc (x, (mp_size_t) 20);
mpz_realloc (y, (mp_size_t) 20);
/* 0 cmp 0, junk in low limbs */
SET1 (x,0, 123);
SET1 (y,0, 456);
check_all (x, y, 0, 0);
/* 123 cmp 0 */
SET1 (x,1, 123);
SET1 (y,0, 456);
check_all (x, y, 1, 1);
/* 123:456 cmp 0 */
SET2 (x,2, 456,123);
SET1 (y,0, 9999);
check_all (x, y, 1, 1);
/* 123 cmp 123 */
SET1(x,1, 123);
SET1(y,1, 123);
check_all (x, y, 0, 0);
/* -123 cmp 123 */
SET1(x,-1, 123);
SET1(y,1, 123);
check_all (x, y, -1, 0);
/* 123 cmp 456 */
SET1(x,1, 123);
SET1(y,1, 456);
check_all (x, y, -1, -1);
/* -123 cmp 456 */
SET1(x,-1, 123);
SET1(y,1, 456);
check_all (x, y, -1, -1);
/* 123 cmp -456 */
SET1(x,1, 123);
SET1(y,-1, 456);
check_all (x, y, 1, -1);
/* 1:0 cmp 1:0 */
SET2 (x,2, 1,0);
SET2 (y,2, 1,0);
check_all (x, y, 0, 0);
/* -1:0 cmp 1:0 */
SET2 (x,-2, 1,0);
SET2 (y,2, 1,0);
check_all (x, y, -1, 0);
/* 2:0 cmp 1:0 */
SET2 (x,2, 2,0);
SET2 (y,2, 1,0);
check_all (x, y, 1, 1);
/* 4:3:2:1 cmp 2:1 */
SET4 (x,4, 4,3,2,1);
SET2 (y,2, 2,1);
check_all (x, y, 1, 1);
/* -4:3:2:1 cmp 2:1 */
SET4 (x,-4, 4,3,2,1);
SET2 (y,2, 2,1);
check_all (x, y, -1, 1);
mpz_clear (x);
mpz_clear (y);
}
void upx_main(
struct Extent xi,
f_expand *const f_decompress,
int junk,
f_unfilter *const f_unf,
char *envp[],
char *argv[],
int argc
)
{
// file descriptor
int fdo;
// decompression buffer
unsigned char *buf;
char *tmpname;
struct p_info header;
// temporary file name
char tmpname_buf[20];
(void)junk;
//
// ----- Step 0: set /proc/self using /proc/<pid> -----
//
//personality(PER_LINUX);
//
// ----- Step 1: prepare input file -----
//
// Read header.
{
register char *__d0, *__d1;
__asm__ __volatile__( "movsl; movsl; movsl"
: "=&D" (__d0), "=&S" (__d1)
: "0" (&header), "1" (xi.buf)
: "memory");
xi.buf = __d1;
xi.size -= sizeof(header);
}
// Paranoia. Make sure this is actually our expected executable
// by checking the random program id. (The id is both stored
// in the header and patched into this stub.)
if (header.p_progid != UPX3)
goto error1;
//
// ----- Step 2: prepare temporary output file -----
//
tmpname = tmpname_buf;
SET4(tmpname + 0, '/', 't', 'm', 'p');
SET4(tmpname + 4, '/', 'u', 'p', 'x');
// Compute name of temporary output file in tmpname[].
// Protect against Denial-of-Service attacks.
{
char *p = tmpname_buf + sizeof(tmpname_buf) - 1;
// Compute the last 4 characters (20 bits) from getpid().
uint32_t r = ascii5(p, (uint32_t)getpid(), 4); *p = '\0'; p -= 4;
// Provide 4 random bytes from our program id.
r ^= header.p_progid;
// Mix in 4 runtime random bytes.
// Don't consume precious bytes from /dev/urandom.
{
#if 1
struct timeval tv;
gettimeofday(&tv, 0);
r ^= (uint32_t) tv.tv_sec;
r ^= ((uint32_t) tv.tv_usec) << 12; // shift into high-bits
#else
// using adjtimex() may cause portability problems
struct timex tx;
adjtimex(&tx);
r ^= (uint32_t) tx.time.tv_sec;
r ^= ((uint32_t) tx.time.tv_usec) << 12; // shift into high-bits
r ^= (uint32_t) tx.errcnt;
#endif
}
// Compute 7 more characters from the 32 random bits.
ascii5(p, r, 7);
}
// Just in case, remove the file.
{
int err = unlink(tmpname);
if (err != -ENOENT && err != 0)
goto error1;
}
// Create the temporary output file.
#if (USE_MMAP_FO)
fdo = open(tmpname, O_RDWR | O_CREAT | O_EXCL, 0700);
#else
fdo = open(tmpname, O_WRONLY | O_CREAT | O_EXCL, 0700);
#endif
#if 0
// Save some bytes of code - the ftruncate() below will fail anyway.
if (fdo < 0)
goto error;
#endif
// Set expected uncompressed file size.
if (ftruncate(fdo, header.p_filesize) != 0)
goto error;
//
// ----- Step 3: setup memory -----
//
#if (USE_MMAP_FO)
// FIXME: packer could set length
buf = (unsigned char *)mmap(0, header.p_filesize,
PROT_READ | PROT_WRITE, MAP_SHARED, fdo, 0);
if ((unsigned long) buf >= (unsigned long) -4095)
goto error;
// Decompressor can overrun the output by 3 bytes.
// Defend against SIGSEGV by using a scratch page.
// FIXME: packer could set address delta
mmap(buf + (PAGE_MASK & (header.p_filesize + ~PAGE_MASK)),
-PAGE_MASK, PROT_READ | PROT_WRITE,
MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0 );
#else
// Temporary decompression buffer.
// FIXME: packer could set length
buf = mmap(0, (header.p_blocksize + OVERHEAD + ~PAGE_MASK) & PAGE_MASK,
PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0 );
if ((unsigned long) buf >= (unsigned long) -4095)
goto error;
#endif
//
// ----- Step 4: decompress blocks -----
//
for (;;)
{
struct b_info h;
// Read and check block sizes.
{
register char *__d0, *__d1;
__asm__ __volatile__( "movsl; movsl; movsl"
: "=&D" (__d0), "=&S" (__d1)
: "0" (&h), "1" (xi.buf)
: "memory");
xi.buf = __d1;
xi.size -= sizeof(h);
}
if (h.sz_unc == 0) // uncompressed size 0 -> EOF
{
if (h.sz_cpr != UPX_MAGIC_LE32) // h.sz_cpr must be h->magic
goto error;
if (header.p_filesize != 0) // all bytes must be written
goto error;
break;
}
// Note: if sz_unc == sz_cpr then the block was not
// compressible and is stored in its uncompressed form.
if (h.sz_cpr > h.sz_unc || h.sz_cpr > header.p_blocksize)
goto error;
// Now we have:
// assert(h.sz_cpr <= h.sz_unc);
// assert(h.sz_unc > 0 && h.sz_unc <= blocksize);
// assert(h.sz_cpr > 0 && h.sz_cpr <= blocksize);
if (h.sz_cpr < h.sz_unc) { // Decompress block.
nrv_uint out_len = h.sz_unc; // EOF for lzma
int i = (*f_decompress)((unsigned char *)xi.buf, h.sz_cpr, buf,
&out_len, *(int *)(void *)&h.b_method);
if (i != 0 || out_len != (nrv_uint)h.sz_unc)
goto error;
// Right now, unfilter is combined with decompression.
// (*f_unfilter)(buf, out_len, cto8);
(void)f_unf;
}
else
{
// Incompressible block
#if (USE_MMAP_FO)
//memcpy(buf, xi.buf, h.sz_unc);
register unsigned long int __d0, __d1, __d2;
__asm__ __volatile__( "rep; movsb"
: "=&c" (__d0), "=&D" (__d1), "=&S" (__d2)
: "0" (h.sz_unc), "1" (buf), "2" (xi.buf)
: "memory");
#endif
}
#if (USE_MMAP_FO)
// unmap part of the output
munmap(buf, h.sz_unc);
buf += h.sz_unc;
#else
// write output file
if (xwrite(fdo, buf, h.sz_unc) != 0)
goto error;
#endif
header.p_filesize -= h.sz_unc;
xi.buf += h.sz_cpr;
xi.size -= h.sz_cpr;
if (xi.size < 0) {
// error exit is here in the middle to keep the jumps short.
error:
(void) unlink(tmpname);
error1:
// Note: the kernel will close all open files and
// unmap any allocated memory.
for (;;)
(void) exit(127);
}
}
//
// ----- Step 5: release resources -----
//
#if !(USE_MMAP_FO)
// Free our temporary decompression buffer.
munmap(buf, malloc_args.ma_length);
#endif
if (close(fdo) != 0)
goto error;
//
// ----- Step 6: try to start program via /proc/self/fd/X -----
//
// Many thanks to Andi Kleen <*****@*****.**> and
// Jamie Lokier <*****@*****.**> for this nice idea.
if (0 > go_self(tmpname, argv, envp))
goto error;
//
// ----- Step 7: start program in /tmp -----
//
// Fork off a subprocess to clean up.
// We have to do this double-fork trick to keep a zombie from
// hanging around if the spawned original program doesn't check for
// subprocesses (as well as to prevent the real program from getting
// confused about this subprocess it shouldn't have).
// Thanks to Adam Ierymenko <*****@*****.**> for this solution.
if (fork() == 0)
{
if (fork() == 0)
{
// Sleep 3 seconds, then remove the temp file.
struct timespec ts; ts.tv_sec = UPX4; ts.tv_nsec = 0;
nanosleep(&ts, 0);
unlink(tmpname);
}
exit(0);
}
// Wait for the first fork()'d process to die.
waitpid(-1, (int *)0, 0);
// Execute the original program.
(void)argc;
execve(tmpname, argv, envp);
//
// ----- Step 8: error exit -----
//
// If we return from execve() there was an error. Give up.
goto error;
}
void
check_various (void)
{
mpq_t x, y;
mpq_init (x);
mpq_init (y);
mpz_realloc (mpq_numref(x), (mp_size_t) 20);
mpz_realloc (mpq_denref(x), (mp_size_t) 20);
mpz_realloc (mpq_numref(y), (mp_size_t) 20);
mpz_realloc (mpq_denref(y), (mp_size_t) 20);
/* 0 == 0 */
SET4 (x, 0,13,12,11,10, 1,23,22,21,1);
SET4 (y, 0,33,32,31,30, 1,43,42,41,1);
check_all (x, y, 1);
/* 83/99 == 83/99 */
SET4 (x, 1,13,12,11,83, 1,23,22,21,99);
SET4 (y, 1,33,32,31,83, 1,43,42,41,99);
check_all (x, y, 1);
/* 1:2:3:4/5:6:7 == 1:2:3:4/5:6:7 */
SET4 (x, 4,1,2,3,4, 3,88,5,6,7);
SET4 (y, 4,1,2,3,4, 3,99,5,6,7);
check_all (x, y, 1);
/* various individual changes making != */
SET4 (x, 4,1,2,3,667, 3,88,5,6,7);
SET4 (y, 4,1,2,3,4, 3,99,5,6,7);
check_all (x, y, 0);
SET4 (x, 4,1,2,666,4, 3,88,5,6,7);
SET4 (y, 4,1,2,3,4, 3,99,5,6,7);
check_all (x, y, 0);
SET4 (x, 4,1,666,3,4, 3,88,5,6,7);
SET4 (y, 4,1,2,3,4, 3,99,5,6,7);
check_all (x, y, 0);
#if GMP_NUMB_BITS != 62
SET4 (x, 4,667,2,3,4, 3,88,5,6,7);
SET4 (y, 4,1,2,3,4, 3,99,5,6,7);
check_all (x, y, 0);
#endif
SET4 (x, 4,1,2,3,4, 3,88,5,6,667);
SET4 (y, 4,1,2,3,4, 3,99,5,6,7);
check_all (x, y, 0);
SET4 (x, 4,1,2,3,4, 3,88,5,667,7);
SET4 (y, 4,1,2,3,4, 3,99,5,6,7);
check_all (x, y, 0);
SET4 (x, 4,1,2,3,4, 3,88,666,6,7);
SET4 (y, 4,1,2,3,4, 3,99,5,6,7);
check_all (x, y, 0);
SET4 (x, -4,1,2,3,4, 3,88,5,6,7);
SET4 (y, 4,1,2,3,4, 3,99,5,6,7);
check_all (x, y, 0);
SET4 (x, 1,1,2,3,4, 3,88,5,6,7);
SET4 (y, 4,1,2,3,4, 3,99,5,6,7);
check_all (x, y, 0);
mpq_clear (x);
mpq_clear (y);
}
//gfd*
static void md5_process(mir_md5_state_t *pms, const mir_md5_byte_t *data /*[64]*/)
{
mir_md5_word_t
a = pms->abcd[0], b = pms->abcd[1],
c = pms->abcd[2], d = pms->abcd[3];
mir_md5_word_t t;
/* Define storage for little-endian or both types of CPUs. */
mir_md5_word_t xbuf[16];
const mir_md5_word_t *X;
{
/*
* Determine dynamically whether this is a big-endian or
* little-endian machine, since we can use a more efficient
* algorithm on the latter.
*/
static const int w = 1;
if (*((const mir_md5_byte_t *)&w)) /* dynamic little-endian */
{
/*
* On little-endian machines, we can process properly aligned
* data without copying it.
*/
if (!((data - (const mir_md5_byte_t *)0) & 3)) {
/* data are properly aligned */
X = (const mir_md5_word_t *)data;
} else {
/* not aligned */
memcpy(xbuf, data, 64);
X = xbuf;
}
}
else /* dynamic big-endian */
{
/*
* On big-endian machines, we must arrange the bytes in the
* right order.
*/
const mir_md5_byte_t *xp = data;
int i;
X = xbuf; /* (dynamic only) */
for (i = 0; i < 16; ++i, xp += 4)
xbuf[i] = xp[0] + (xp[1] << 8) + (xp[2] << 16) + (xp[3] << 24);
}
}
#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32 - (n))))
/* Round 1. */
/* Let [abcd k s i] denote the operation
a = b + ((a + F(b,c,d) + X[k] + T[i]) <<< s). */
#define F(x, y, z) (((x) & (y)) | (~(x) & (z)))
#define SET1(a, b, c, d, k, s, Ti)\
t = a + F(b,c,d) + X[k] + Ti;\
a = ROTATE_LEFT(t, s) + b
/* Do the following 16 operations. */
SET1(a, b, c, d, 0, 7, T1);
SET1(d, a, b, c, 1, 12, T2);
SET1(c, d, a, b, 2, 17, T3);
SET1(b, c, d, a, 3, 22, T4);
SET1(a, b, c, d, 4, 7, T5);
SET1(d, a, b, c, 5, 12, T6);
SET1(c, d, a, b, 6, 17, T7);
SET1(b, c, d, a, 7, 22, T8);
SET1(a, b, c, d, 8, 7, T9);
SET1(d, a, b, c, 9, 12, T10);
SET1(c, d, a, b, 10, 17, T11);
SET1(b, c, d, a, 11, 22, T12);
SET1(a, b, c, d, 12, 7, T13);
SET1(d, a, b, c, 13, 12, T14);
SET1(c, d, a, b, 14, 17, T15);
SET1(b, c, d, a, 15, 22, T16);
/* Round 2. */
/* Let [abcd k s i] denote the operation
a = b + ((a + G(b,c,d) + X[k] + T[i]) <<< s). */
#define G(x, y, z) (((x) & (z)) | ((y) & ~(z)))
#define SET2(a, b, c, d, k, s, Ti)\
t = a + G(b,c,d) + X[k] + Ti;\
a = ROTATE_LEFT(t, s) + b
/* Do the following 16 operations. */
SET2(a, b, c, d, 1, 5, T17);
SET2(d, a, b, c, 6, 9, T18);
SET2(c, d, a, b, 11, 14, T19);
SET2(b, c, d, a, 0, 20, T20);
SET2(a, b, c, d, 5, 5, T21);
SET2(d, a, b, c, 10, 9, T22);
SET2(c, d, a, b, 15, 14, T23);
SET2(b, c, d, a, 4, 20, T24);
SET2(a, b, c, d, 9, 5, T25);
SET2(d, a, b, c, 14, 9, T26);
SET2(c, d, a, b, 3, 14, T27);
SET2(b, c, d, a, 8, 20, T28);
SET2(a, b, c, d, 13, 5, T29);
SET2(d, a, b, c, 2, 9, T30);
SET2(c, d, a, b, 7, 14, T31);
SET2(b, c, d, a, 12, 20, T32);
/* Round 3. */
/* Let [abcd k s t] denote the operation
a = b + ((a + H(b,c,d) + X[k] + T[i]) <<< s). */
#define H(x, y, z) ((x) ^ (y) ^ (z))
#define SET3(a, b, c, d, k, s, Ti)\
t = a + H(b,c,d) + X[k] + Ti;\
a = ROTATE_LEFT(t, s) + b
/* Do the following 16 operations. */
SET3(a, b, c, d, 5, 4, T33);
SET3(d, a, b, c, 8, 11, T34);
SET3(c, d, a, b, 11, 16, T35);
SET3(b, c, d, a, 14, 23, T36);
SET3(a, b, c, d, 1, 4, T37);
SET3(d, a, b, c, 4, 11, T38);
SET3(c, d, a, b, 7, 16, T39);
SET3(b, c, d, a, 10, 23, T40);
SET3(a, b, c, d, 13, 4, T41);
SET3(d, a, b, c, 0, 11, T42);
SET3(c, d, a, b, 3, 16, T43);
SET3(b, c, d, a, 6, 23, T44);
SET3(a, b, c, d, 9, 4, T45);
SET3(d, a, b, c, 12, 11, T46);
SET3(c, d, a, b, 15, 16, T47);
SET3(b, c, d, a, 2, 23, T48);
/* Round 4. */
/* Let [abcd k s t] denote the operation
a = b + ((a + I(b,c,d) + X[k] + T[i]) <<< s). */
#define I(x, y, z) ((y) ^ ((x) | ~(z)))
#define SET4(a, b, c, d, k, s, Ti)\
t = a + I(b,c,d) + X[k] + Ti;\
a = ROTATE_LEFT(t, s) + b
/* Do the following 16 operations. */
SET4(a, b, c, d, 0, 6, T49);
SET4(d, a, b, c, 7, 10, T50);
SET4(c, d, a, b, 14, 15, T51);
SET4(b, c, d, a, 5, 21, T52);
SET4(a, b, c, d, 12, 6, T53);
SET4(d, a, b, c, 3, 10, T54);
SET4(c, d, a, b, 10, 15, T55);
SET4(b, c, d, a, 1, 21, T56);
SET4(a, b, c, d, 8, 6, T57);
SET4(d, a, b, c, 15, 10, T58);
SET4(c, d, a, b, 6, 15, T59);
SET4(b, c, d, a, 13, 21, T60);
SET4(a, b, c, d, 4, 6, T61);
SET4(d, a, b, c, 11, 10, T62);
SET4(c, d, a, b, 2, 15, T63);
SET4(b, c, d, a, 9, 21, T64);
/* Then perform the following additions. (That is increment each
of the four registers by the value it had before this block
was started.) */
pms->abcd[0] += a;
pms->abcd[1] += b;
pms->abcd[2] += c;
pms->abcd[3] += d;
}
/* Enable the controller to accept connections */
static jresult_t dcd_enable(jdevice_t dev, jbool_t is_full_speed)
{
td243fc_rev2_softc_t *sc = (td243fc_rev2_softc_t *)j_device_get_softc(dev);
jresult_t rc;
__VOLATILE__ juint32_t v;
DBG_I(DSLAVE_DCD, ("DCD: dcd_enable\n"));
rc = jinterrupt_setup(sc->irq_res, dcd_intr, sc, dcd_soft_intr, sc,
&sc->interrupt_h);
if (rc)
return rc;
sc->is_suspend = 0;
sc->free_mem_start = 0;
/* Allocate buffers for EP0 IN and OUT */
sc->ep[0].buf_size = TD243FC_EP0_MAX_PACKET_SIZE;
sc->ep[1].buf_size = TD243FC_EP0_MAX_PACKET_SIZE;
sc->pendig_address = FALSE;
sc->address = 0;
sc->add_to_list = FALSE;
sc->ep_ready = 0;
rc = td243fc_mem_alloc(sc, sc->ep[0].buf_size, &sc->ep[0].xaddr);
KASSERT(!rc, ("Can't alloc buffers for EP0 X-OUT\n"));
rc = td243fc_mem_alloc(sc, sc->ep[0].buf_size, &sc->ep[0].yaddr);
KASSERT(!rc, ("Can't alloc buffers for EP0 Y-OUT\n"));
rc = td243fc_mem_alloc(sc, sc->ep[1].buf_size, &sc->ep[1].xaddr);
KASSERT(!rc, ("Can't alloc buffers for EP0 X-IN\n"));
rc = td243fc_mem_alloc(sc, sc->ep[1].buf_size, &sc->ep[1].yaddr);
KASSERT(!rc, ("Can't alloc buffers for EP0 Y-IN\n"));
/* Disable Chip level interrupt */
WRITE4(TD243FC_CHIP_INT_ENABLE_REG, 0);
/* System interrupts init */
WRITE4(TD243FC_SYSTEM_INT_ENABLE_REG, 0);
/* Clear interrupts */
v = READ4(TD243FC_SYSTEM_INT_STATUS_REG);
WRITE4(TD243FC_SYSTEM_INT_STATUS_REG, v);
sc->sys_intr_mask = (TD243FC_BUSRST | TD243FC_SUSP);
WRITE4(TD243FC_SYSTEM_INT_ENABLE_REG, sc->sys_intr_mask);
/* Disable and clear all endpoint done interrupts */
sc->ep_intr_mask = 0;
WRITE4(TD243FC_EP_DONE_ENABLE_REG, sc->ep_intr_mask);
WRITE4(TD243FC_EP_DONE_STATUS_REG, 0xffffffff);
/* Zero the address */
WRITE4(TD243FC_DEVICEADDRESS_REG, BFSET4(TD243FC_DEVADDR, 0x0));
/* Clear all EpDma channels */
WRITE4(TD243FC_DMA_EP_ENABLE_REG, 0x0);
WRITE4(TD243FC_DMA_INTR_STATUS_REG, TD243FC_DMA_EPERR);
WRITE4(TD243FC_DMA_EP_ERROR_STATUS_REG, TD243FC_DMA_EPERR);
/* Enable device controller interrupts */
SET4(TD243FC_CHIP_INT_ENABLE_REG, TD243FC_INTF);
return 0;
}
static void dcd_soft_intr(void *arg)
{
td243fc_rev2_softc_t *sc = (td243fc_rev2_softc_t *)arg;
juint32_t sys_intr, ep_intr;
juint32_t fc_cmd;
DBG_V(DSLAVE_DCD, ("DCD: dcd_soft_intr\n"));
jspinlock_lock(sc->sc_lock);
{
sys_intr = sc->sys_intr;
ep_intr = sc->ep_intr;
fc_cmd = sc->fc_cmd;
sc->sys_intr = sc->ep_intr = sc->fc_cmd = 0;
}
jspinlock_unlock(sc->sc_lock);
sys_intr &= sc->sys_intr_mask;
ep_intr &= sc->ep_intr_mask;
/* Acknowledge the interuppts */
WRITE4(TD243FC_SYSTEM_INT_STATUS_REG, sys_intr);
/* HSU Addition */
/* Handle EP interrupts first. Fix for the case where OUT EP interrupt and
subsequent RESET interrupt are handled together. So the OUT EP interrupt
has to be handled first. The opposite case was not observed. */
if (sys_intr & TD243FC_DONEREG)
{
juint_t i;
sc->add_to_list = TRUE;
/* Handle interrupts on EP0 (IN and OUT interrupts) */
if (ep_intr & (TD243FC_EP_BIT(0, 0) | TD243FC_EP_BIT(0, 1)))
handle_ep0(sc, ep_intr);
/* Handle interrupts on endpoints other than EP0 */
for (i = 2; i < TD243FC_EP_NUM * 2; i++)
{
if (ep_intr & (1<<i))
handle_epn(sc, i);
}
/* Clear interrupts of handled EPs */
WRITE4(TD243FC_EP_DONE_STATUS_REG, ep_intr);
sc->add_to_list = FALSE;
if (sc->ep_ready)
{
WRITE4(TD243FC_EP_READY_REG, sc->ep_ready);
sc->ep_ready = 0;
}
}
/* HSU End */
if ((sys_intr & TD243FC_BUSRST) && (fc_cmd & TD243FC_RESETDET))
{
DBG_V(DSLAVE_DCD, ("DCD: Bus reset detected\n"));
handle_reset(sc);
/* Since we enable interrupts other then BUSRST only in handle_reset,
* no need to handle other interrupts together with BUSRST */
goto Exit;
}
if ((sys_intr & TD243FC_RESUME) && (fc_cmd & TD243FC_RSMINPROG))
{
if (sc->is_suspend)
{
DBG_V(DSLAVE_DCD, ("DCD: RESUME detected\n"));
core_resume(sc->core_ctx);
sc->is_suspend = 0;
sc->sys_intr_mask &= ~TD243FC_RESUME;
sc->sys_intr_mask |= TD243FC_SUSP;
WRITE4(TD243FC_SYSTEM_INT_ENABLE_REG, sc->sys_intr_mask);
}
}
if ((sys_intr & TD243FC_SUSP) && (fc_cmd & TD243FC_SUSPDET))
{
if (!sc->is_suspend)
{
DBG_V(DSLAVE_DCD, ("DCD: SUSPEND detected\n"));
core_suspend(sc->core_ctx);
sc->is_suspend = 1;
sc->sys_intr_mask &= ~TD243FC_SUSP;
sc->sys_intr_mask |= TD243FC_RESUME;
WRITE4(TD243FC_SYSTEM_INT_ENABLE_REG, sc->sys_intr_mask);
SET4(TD243FC_COMMAND_REG, TD243FC_SUSPDET);
}
}
/* HSU Addition */
/* Moved handling of TD243FC_DONEREG interrupt from here to the beginning
of the function */
/* HSU End */
WRITE4(TD243FC_SYSTEM_INT_ENABLE_REG, sc->sys_intr_mask);
Exit:
/* Ack & Enable device controller global interrupt */
SET4(TD243FC_CHIP_INT_ENABLE_REG, TD243FC_INTF);
DBG_V(DSLAVE_DCD, ("DCD: dcd_soft_intr finished\n\n\n"));
}
