static void setup_int (SIM_CPU *current_cpu, PCADDR pc) { USI ssp = fr30bf_h_dr_get (current_cpu, H_DR_SSP); USI ps = fr30bf_h_ps_get (current_cpu); ssp -= 4; SETMEMSI (current_cpu, pc, ssp, ps); ssp -= 4; SETMEMSI (current_cpu, pc, ssp, pc + 2); fr30bf_h_dr_set (current_cpu, H_DR_SSP, ssp); fr30bf_h_sbit_set (current_cpu, 0); }
/* Perform a software reset. */ void frv_software_reset (SIM_CPU *cpu) { /* GR, FR and CPR registers are undefined at software reset. */ frv_reset_spr (cpu); /* Reset the RSTR register (in memory). */ if (frv_cache_enabled (CPU_DATA_CACHE (cpu))) frvbf_mem_set_SI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_SOFTWARE_RESET); else SETMEMSI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_SOFTWARE_RESET); }
/* Perform a power on reset. */ void frv_power_on_reset (SIM_CPU *cpu) { /* GR, FR and CPR registers are undefined at initialization time. */ frv_initialize_spr (cpu); /* Initialize the RSTR register (in memory). */ if (frv_cache_enabled (CPU_DATA_CACHE (cpu))) frvbf_mem_set_SI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_INITIAL_VALUE); else SETMEMSI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_INITIAL_VALUE); }
/* Perform a hardware reset. */ void frv_hardware_reset (SIM_CPU *cpu) { /* GR, FR and CPR registers are undefined at hardware reset. */ frv_initialize_spr (cpu); /* Reset the RSTR register (in memory). */ if (frv_cache_enabled (CPU_DATA_CACHE (cpu))) frvbf_mem_set_SI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_HARDWARE_RESET); else SETMEMSI (cpu, CPU_PC_GET (cpu), RSTR_ADDRESS, RSTR_HARDWARE_RESET); /* Reset the insn and data caches. */ frv_cache_invalidate_all (CPU_INSN_CACHE (cpu), 0/* no flush */); frv_cache_invalidate_all (CPU_DATA_CACHE (cpu), 0/* no flush */); }
static SEM_PC SEM_FN_NAME (lm32bf,sw) (SIM_CPU *current_cpu, SEM_ARG sem_arg) { #define FLD(f) abuf->fields.sfmt_addi.f ARGBUF *abuf = SEM_ARGBUF (sem_arg); int UNUSED written = 0; IADDR UNUSED pc = abuf->addr; SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); { SI opval = CPU (h_gr[FLD (f_r1)]); SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[FLD (f_r0)]), EXTHISI (TRUNCSIHI (FLD (f_imm)))), opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); } return vpc; #undef FLD }
/* Execute a write stored on the write queue. */ void cgen_write_queue_element_execute (SIM_CPU *cpu, CGEN_WRITE_QUEUE_ELEMENT *item) { IADDR pc; switch (CGEN_WRITE_QUEUE_ELEMENT_KIND (item)) { case CGEN_BI_WRITE: *item->kinds.bi_write.target = item->kinds.bi_write.value; break; case CGEN_QI_WRITE: *item->kinds.qi_write.target = item->kinds.qi_write.value; break; case CGEN_SI_WRITE: *item->kinds.si_write.target = item->kinds.si_write.value; break; case CGEN_SF_WRITE: *item->kinds.sf_write.target = item->kinds.sf_write.value; break; case CGEN_PC_WRITE: CPU_PC_SET (cpu, item->kinds.pc_write.value); break; case CGEN_FN_HI_WRITE: item->kinds.fn_hi_write.function (cpu, item->kinds.fn_hi_write.regno, item->kinds.fn_hi_write.value); break; case CGEN_FN_SI_WRITE: item->kinds.fn_si_write.function (cpu, item->kinds.fn_si_write.regno, item->kinds.fn_si_write.value); break; case CGEN_FN_SF_WRITE: item->kinds.fn_sf_write.function (cpu, item->kinds.fn_sf_write.regno, item->kinds.fn_sf_write.value); break; case CGEN_FN_DI_WRITE: item->kinds.fn_di_write.function (cpu, item->kinds.fn_di_write.regno, item->kinds.fn_di_write.value); break; case CGEN_FN_DF_WRITE: item->kinds.fn_df_write.function (cpu, item->kinds.fn_df_write.regno, item->kinds.fn_df_write.value); break; case CGEN_FN_XI_WRITE: item->kinds.fn_xi_write.function (cpu, item->kinds.fn_xi_write.regno, item->kinds.fn_xi_write.value); break; case CGEN_FN_PC_WRITE: item->kinds.fn_pc_write.function (cpu, item->kinds.fn_pc_write.value); break; case CGEN_MEM_QI_WRITE: pc = item->insn_address; SETMEMQI (cpu, pc, item->kinds.mem_qi_write.address, item->kinds.mem_qi_write.value); break; case CGEN_MEM_HI_WRITE: pc = item->insn_address; SETMEMHI (cpu, pc, item->kinds.mem_hi_write.address, item->kinds.mem_hi_write.value); break; case CGEN_MEM_SI_WRITE: pc = item->insn_address; SETMEMSI (cpu, pc, item->kinds.mem_si_write.address, item->kinds.mem_si_write.value); break; case CGEN_MEM_DI_WRITE: pc = item->insn_address; SETMEMDI (cpu, pc, item->kinds.mem_di_write.address, item->kinds.mem_di_write.value); break; case CGEN_MEM_DF_WRITE: pc = item->insn_address; SETMEMDF (cpu, pc, item->kinds.mem_df_write.address, item->kinds.mem_df_write.value); break; case CGEN_MEM_XI_WRITE: pc = item->insn_address; SETMEMSI (cpu, pc, item->kinds.mem_xi_write.address, item->kinds.mem_xi_write.value[0]); SETMEMSI (cpu, pc, item->kinds.mem_xi_write.address + 4, item->kinds.mem_xi_write.value[1]); SETMEMSI (cpu, pc, item->kinds.mem_xi_write.address + 8, item->kinds.mem_xi_write.value[2]); SETMEMSI (cpu, pc, item->kinds.mem_xi_write.address + 12, item->kinds.mem_xi_write.value[3]); break; case CGEN_FN_MEM_QI_WRITE: pc = item->insn_address; item->kinds.fn_mem_qi_write.function (cpu, pc, item->kinds.fn_mem_qi_write.address, item->kinds.fn_mem_qi_write.value); break; case CGEN_FN_MEM_HI_WRITE: pc = item->insn_address; item->kinds.fn_mem_hi_write.function (cpu, pc, item->kinds.fn_mem_hi_write.address, item->kinds.fn_mem_hi_write.value); break; case CGEN_FN_MEM_SI_WRITE: pc = item->insn_address; item->kinds.fn_mem_si_write.function (cpu, pc, item->kinds.fn_mem_si_write.address, item->kinds.fn_mem_si_write.value); break; case CGEN_FN_MEM_DI_WRITE: pc = item->insn_address; item->kinds.fn_mem_di_write.function (cpu, pc, item->kinds.fn_mem_di_write.address, item->kinds.fn_mem_di_write.value); break; case CGEN_FN_MEM_DF_WRITE: pc = item->insn_address; item->kinds.fn_mem_df_write.function (cpu, pc, item->kinds.fn_mem_df_write.address, item->kinds.fn_mem_df_write.value); break; case CGEN_FN_MEM_XI_WRITE: pc = item->insn_address; item->kinds.fn_mem_xi_write.function (cpu, pc, item->kinds.fn_mem_xi_write.address, item->kinds.fn_mem_xi_write.value); break; default: abort (); break; /* FIXME: for now....print message later. */ } }