static void timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
unsigned short ctl=TIMER_INTERRUPT;
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
interval = (PIU_TIMER_FREQ_KHZ*1000 / HZ) ;
OUTREG16(clkevt_base + ADDR_TIMER_MAX_LOW, (interval &0xffff));
OUTREG16(clkevt_base + ADDR_TIMER_MAX_HIGH, (interval >>16));
ctl|=TIMER_ENABLE;
SETREG16(clkevt_base, ctl);
break;
case CLOCK_EVT_MODE_ONESHOT:
/* period set, and timer enabled in 'next_event' hook */
ctl|=TIMER_TRIG;
SETREG16(clkevt_base, ctl);
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
default:
break;
}
}
void __init edison_init_timer(void)
{
#if 1 //calculate mult and shift for sched_clock
u32 shift,mult;
#endif
#ifdef CONFIG_MSTAR_EDISON_BD_FPGA
GLB_TIMER_FREQ_KHZ= 24*1000 ; // PERIPHCLK = CPU Clock / 2,
// div 2 later,when CONFIG_GENERIC_CLOCKEVENTS
// clock event will handle this value
//clock event will handle this value
#else
GLB_TIMER_FREQ_KHZ=(query_frequency()*1000/2); // PERIPHCLK = CPU Clock / 2
// div 2 later,when CONFIG_GENERIC_CLOCKEVENTS
// clock event will handle this value
#endif
printk("Global Timer Frequency = %d MHz\n",GLB_TIMER_FREQ_KHZ/1000);
printk("CPU Clock Frequency = %d MHz\n",query_frequency());
#ifdef CONFIG_HAVE_SCHED_CLOCK
#if 1 //calculate mult and shift for sched_clock
clocks_calc_mult_shift(&mult, &shift, (u32)(GLB_TIMER_FREQ_KHZ*1000), NSEC_PER_SEC,0);
printk("fre = %d, mult= %u, shift= %u\n",(GLB_TIMER_FREQ_KHZ*1000),mult,shift);
SC_SHIFT=shift;
SC_MULT=mult;
#endif
mstar_sched_clock_init((void __iomem *)(PERI_VIRT+0x200), (unsigned long)(GLB_TIMER_FREQ_KHZ*1000));
#endif
#ifdef CONFIG_GENERIC_CLOCKEVENTS
//mstar_local_timer_init(((void __iomem *)PERI_ADDRESS(PERI_PHYS+0x600))); //private_timer base
edison_clocksource_init(EDISON_BASE_REG_TIMER1_PA);
edison_clockevents_init(INT_WDT_IRQ);
#else
setup_irq(E_FIQ_EXTIMER0 , &edison_timer_irq);
//enable timer interrupt
SETREG16(EDISON_BASE_REG_TIMER0_PA,TIMER_INTERRUPT);
//set interval
interval = ( 12*1000*1000 ) / HZ ;
OUTREG16(EDISON_BASE_REG_TIMER0_PA + ADDR_TIMER_MAX_LOW, (interval & 0xffff));
OUTREG16(EDISON_BASE_REG_TIMER0_PA + ADDR_TIMER_MAX_HIGH, (interval >>16));
//trig timer0
SETREG16(EDISON_BASE_REG_TIMER0_PA, TIMER_TRIG);
#endif
}
void __init chip_clocksource_init(unsigned int base)
{
struct clocksource *cs = &clocksource_timer;
clksrc_base = base;
#if USE_GLOBAL_TIMER
PERI_W(GT_CONTROL,0x1); //Enable
//calculate the value of mult //cycle= ( time(ns) *mult ) >> shift
cs->mult = clocksource_khz2mult(GLB_TIMER_FREQ_KHZ, cs->shift);//PERICLK = CPUCLK/2
#else
/* setup timer 1 as free-running clocksource */
//make sure timer 1 is disable
CLRREG16(clksrc_base, TIMER_ENABLE);
//set max period
OUTREG16(clksrc_base+(0x2<<2),0xffff);
OUTREG16(clksrc_base+(0x3<<2),0xffff);
//enable timer 1
SETREG16(clksrc_base, TIMER_ENABLE);
// TODO: need to double check
//calculate the value of mult //cycle= ( time(ns) *mult ) >> shift
cs->mult = clocksource_khz2mult(GLB_TIMER_FREQ_KHZ, cs->shift); //Mstar timer =>12Mhz,
#endif
clocksource_register(cs);
}
void hw_reset(void)
{
printf("hw_reset\n");
OUTREG16(A_WDT_TCSR, WDT_CLK_EXTAL);
SETREG16(A_WDT_TCSR, WDT_CLK_PRESCALE_CLK1024);
OUTREG16(A_WDT_TDR, 3);
OUTREG16(A_WDT_TCNT, 0);
SETREG8(A_WDT_TCER, WDT_ENABLE);
while (1);
}
static int timer_set_next_event(unsigned long next, struct clock_event_device *evt)
{
//stop timer
//OUTREG16(clkevt_base, 0x0);
//set period
OUTREG16(clkevt_base + ADDR_TIMER_MAX_LOW, (next &0xffff));
OUTREG16(clkevt_base + ADDR_TIMER_MAX_HIGH, (next >>16));
//enable timer
SETREG16(clkevt_base, TIMER_TRIG|TIMER_INTERRUPT);//default
return 0;
}
void
ACAudioHWContext::HWEnableOutputChannel(BOOL fEnable)
{
DEBUGMSG(ZONE_AC,(L"AC: HWEnableOutputChannel (%x)\r\n", fEnable));
// enable or disable the transmitter
if (fEnable)
{
SETREG16(&m_pMCBSPRegisters->usMCBSP_SPCR2, MCBSP_XRST | MCBSP_GRST | MCBSP_FRST);
}
else
{
CLRREG16(&m_pMCBSPRegisters->usMCBSP_SPCR2, MCBSP_XRST);
}
}
void
ACAudioHWContext::HWEnableInputChannel(BOOL fEnable)
{
DEBUGMSG(ZONE_AC,(L"AC: HWEnableInputChannel (%x)\r\n", 1));
// enable or disable the receiver
if (fEnable)
{
SETREG16(&m_pMCBSPRegisters->usMCBSP_SPCR1, MCBSP_RRST);
}
else
{
CLRREG16(&m_pMCBSPRegisters->usMCBSP_SPCR1, MCBSP_RRST);
}
}
static UINT32 am3Register(void)
{
switch (modDim)
{
case 0:
SETREG8(v60.reg[modVal&0x1F], modWriteValB);
break;
case 1:
SETREG16(v60.reg[modVal&0x1F], modWriteValH);
break;
case 2:
v60.reg[modVal&0x1F] = modWriteValW;
break;
}
return 1;
}
static UINT32 am3Register(v60_state *cpustate)
{
switch (cpustate->moddim)
{
case 0:
SETREG8(cpustate->reg[cpustate->modval & 0x1F], cpustate->modwritevalb);
break;
case 1:
SETREG16(cpustate->reg[cpustate->modval & 0x1F], cpustate->modwritevalh);
break;
case 2:
cpustate->reg[cpustate->modval & 0x1F] = cpustate->modwritevalw;
break;
}
return 1;
}
static irqreturn_t chip_timer_interrupt(int irq, void *dev_id)
{
unsigned short tmp;
timer_tick();
//stop timer
CLRREG16(chip_BASE_REG_TIMER0_PA, TIMER_TRIG);
//set interval
//interval = (CLOCK_TICK_RATE / HZ);
OUTREG16(chip_BASE_REG_TIMER0_PA + ADDR_TIMER_MAX_LOW, (interval &0xffff));
OUTREG16(chip_BASE_REG_TIMER0_PA + ADDR_TIMER_MAX_HIGH, (interval >>16));
//trig timer0
SETREG16(chip_BASE_REG_TIMER0_PA, TIMER_TRIG);
return IRQ_HANDLED;
}
VOID
ACAudioHWContext::SetCodecPower(BOOL fPowerOn)
{
DEBUGMSG(ZONE_AC, (L"+ACAudioHWContext::SetCodecPower(%x)\r\n", fPowerOn));
// power on or off the BSP and CODEC
if (fPowerOn)
{
CLRREG16(&m_pMCBSPRegisters->usMCBSP_PCR, MCBSP_IDLEEN);
TSC2101Write(m_hSPI, TSC2101_AUDCTRL_POWER, CPC_SP1PWDN | CPC_SP2PWDN);
}
else
{
TSC2101Write(m_hSPI, TSC2101_AUDCTRL_POWER, CPC_MBIAS_HND | CPC_MBIAS_HED | CPC_ASTPWD |
CPC_SP1PWDN | CPC_SP2PWDN | CPC_DAPWDN | CPC_ADPWDN | CPC_VGPWDN |
CPC_COPWDN | CPC_LSPWDN);
SETREG16(&m_pMCBSPRegisters->usMCBSP_PCR, MCBSP_IDLEEN);
}
}
static UINT32 opDECH(v60_state *cpustate) /* TRUSTED */
{
UINT16 apph;
cpustate->modadd = cpustate->PC + 1;
cpustate->moddim = 1;
cpustate->amlength1 = ReadAMAddress(cpustate);
if (cpustate->amflag)
apph = (UINT16)cpustate->reg[cpustate->amout];
else
apph = cpustate->program->read_word_unaligned(cpustate->amout);
SUBW(apph, 1);
if (cpustate->amflag)
SETREG16(cpustate->reg[cpustate->amout], apph);
else
cpustate->program->write_word_unaligned(cpustate->amout, apph);
return cpustate->amlength1 + 1;
}
UINT32 opDECH(void) /* TRUSTED */
{
UINT16 apph;
modAdd=PC+1;
modDim=1;
amLength1=ReadAMAddress();
if (amFlag)
apph=(UINT16)v60.reg[amOut];
else
apph=MemRead16(amOut);
SUBW(apph, 1);
if (amFlag)
SETREG16(v60.reg[amOut], apph);
else
MemWrite16(amOut, apph);
return amLength1+1;
}
void io_handle(int (*io_read)(), int (*io_write)(), int (*io_pend)(),
void *priv)
{
void *addr;
int err,res;
char c;
int count,rc_count;
w32 qaddr;
int op=(w8)reg[0];
reg[0]=0;
#ifdef IOTEST
printf("call io_handle \t\td0=%d\td1=%x\td2=%x\td3=%x\ta1=%x\n",op,reg[1],reg[2],reg[3],aReg[1]);
#endif
switch (op)
{
case 0:
*reg=(*io_pend)(priv);
break;
case 1:
res=(*io_read)(priv,&c,1);
if (res==1)
*((char*)reg+4+RBO)=c;
else *reg=res ? res: QERR_EOF;
break;
case 2: /* read line */
count=max(0,(uw16)reg[2]-(uw16)reg[1]);
rc_count=(uw16)reg[1];
qaddr=aReg[1];
prepChangeMem(aReg[1],aReg[1]+rc_count);
ioread(io_read,priv,qaddr,&count,true);
//(uw16)reg[1]=count+rc_count;
SETREG16(reg[1], count+rc_count);
aReg[1]=qaddr+count;
break;
case 3: /* fetch string */
qaddr=aReg[1];
count=max(0,(uw16)reg[2]-(uw16)reg[1]);
rc_count=(uw16)reg[1];
prepChangeMem(aReg[1],aReg[1]+rc_count);
ioread(io_read,priv,qaddr,&count,false);
reg[1]=count+rc_count;
aReg[1]=qaddr+count;
break;
case 5:
res=(*io_write)(priv,(Ptr)reg+4+RBO,1);
if (res<0) *reg=res;
break;
case 7: /* send string */
count=(uw16)reg[2];
res=(*io_write)(priv,(Ptr)theROM+aReg[1],count);
if (res<0)
{
count=0;
*reg=res;
} else count=res;
reg[1]=count;
aReg[1]+=count;
break;
case 0x48: /* read file into memory */
qaddr=aReg[1];
count=reg[2];
rc_count=reg[1];
prepChangeMem(aReg[1],aReg[1]+rc_count);
ioread(io_read,priv,qaddr,&count,false);
aReg[1]=qaddr+count;
break;
case 0x49:
count=reg[2];
res=(*io_write)(priv,(Ptr)theROM+aReg[1],count);
if (res<0)
{
count=0;
*reg=res;
} else count=res;
aReg[1]+=count;
break;
default:
*reg=QERR_BP;
break;
}
#ifdef IOTEST
printf("ret from io_handle \td0=%d\td1=%x\t\ta1=%x\n",reg[0],reg[1],aReg[1]);
#endif
}
void mini_ispv1_hw_3a_switch(u8 on)
{
u8 win_top_h,win_top_l;
u8 win_left_h,win_left_l;
u8 win_height;
u8 win_width;
u32 data_count = 0;
#if 0
u8 hdr_movie_on = 0;
#endif
print_info(" %s on = %d",__func__,on);
if(on == HW_3A_ON)
{
#if 0
if (mini_this_ispdata->sensor->sensor_hdr_movie.set_hdr_movie_switch)
{
hdr_movie_on = mini_this_ispdata->sensor->sensor_hdr_movie.get_hdr_movie_switch();
if(hdr_movie_on)
GETREG16(REG_ROI_MEM_WIDTH_3A,data_count);
}
#endif
data_count = data_count + mini_hw_3a_data.data_count;
SETREG16(REG_ROI_MEM_WIDTH_3A,data_count);
win_top_l = mini_hw_3a_data.ae_param.ae_win_top;
win_top_h = mini_hw_3a_data.ae_param.ae_win_top >> 8;
win_left_l = mini_hw_3a_data.ae_param.ae_win_left;
win_left_h = mini_hw_3a_data.ae_param.ae_win_left >> 8;
win_height = mini_hw_3a_data.ae_param.ae_win_height;
win_width = mini_hw_3a_data.ae_param.ae_win_width;
SETREG8(HW_3A_HIST_SHIFT_REG,mini_hw_3a_data.ae_param.ae_hist_shift);//r_hist_shift
SETREG8(HW_3A_MEAN_SHIFT_REG,mini_hw_3a_data.ae_param.ae_mean_shift);//r_mean_shift
//aec agc awb:hist&mean
SETREG8(HW_3A_WIN_TOP_REG_H,win_top_h);//r_window_top[11:8]
SETREG8(HW_3A_WIN_TOP_REG_L,win_top_l);//r_window_top[7:0]
SETREG8(HW_3A_WIN_LEFT_REG_H,win_left_h);//r_window_left[12:8]
SETREG8(HW_3A_WIN_LEFT_REG_L,win_left_l);//r_window_left[7:0]
SETREG8(HW_3A_WIN_HEIGHT_REG,win_height);//r_window_height
SETREG8(HW_3A_WIN_WIDTH_REG,win_width);//r_window_width
SETREG8(HW_3A_BLC_ENABLE_REG, mini_hw_3a_data.blc_enable); //BLC enable
SETREG8(HW_3A_AECAGC_MODEL, mini_hw_3a_data.ae_param.ae_win_model);//aec agc &awb mode 0:16x16;1:8x8
SETREG8(HW_3A_AF_ENABLE_REG, mini_hw_3a_data.af_param.af_enable); //AF stat enable
SETREG8(HW_3A_AECAGC_ENABLE, mini_hw_3a_data.ae_param.ae_enable); //AEC&AGC&AWB stat enable
SETREG8(HW_3A_ROI_ENABLE_REG,0x4);
//SETREG8(HW_3A_FRAME_CTRL_REG,0x05);//ROI smode enable, dual source enable
/* HW_3A_FRAME_CTRL_REG:bit[0 ] ROI smode enable, dual source enable*/
SETREG8(HW_3A_FRAME_CTRL_REG,GETREG8(HW_3A_FRAME_CTRL_REG) | SHIFT_BIT_0);
/*HW_3A_ENABLE bit[7][6]:gamma&tonemapping combined , bit[1]:3A enalbe */
SETREG8(HW_3A_ENABLE, GETREG8(HW_3A_ENABLE) |SHIFT_BIT_1);
//SETREG8(HW_3A_RAM_ACCESS_ENABLE, 0x8);
}
else
{
