exception_t mmu_write(core_t *core, mmu_t *mem, int32_t vaddr, uint32_t src,
mem_op_size_t op_size)
{
/* IO mapped address */
if(vaddr >= IO_REGISTER_AREA) {
LOG("Writing IO register area");
device_t *dev;
/* Iterate over the devices */
for(dev = mem->devices; dev->next != NULL; dev = dev->next) {
if(vaddr >= dev->io_addr_base
&& vaddr <= dev->io_addr_base + dev->io_addr_len) {
dev->io_write(dev, vaddr, src);
}
}
return EXC_None;
/* If writing to descriptor area is not allowed */
} else if(vaddr >= IO_DESCRIPTOR_AREA) {
LOG("Writing IO descriptor area");
return EXC_AddressErrorStore;
}
/* Translate to physical */
uint32_t paddr = translate_vaddr(vaddr);
/* Translate to actual address*/
uint8_t *aaddr = translate_paddr(paddr, mem);
/* write */
if(op_size == MEM_OP_BYTE) {
SET_BIGBYTE(aaddr, src);
} else if(op_size == MEM_OP_HALF) {
SET_BIGHALF(aaddr, src);
} else if(op_size == MEM_OP_WORD) {
SET_BIGWORD(aaddr, src);
}
/*
DEBUG("WRITTEN: 0x%08X to VADDR: 0x%08X, AADDR: %p", *((uint32_t*)aaddr), vaddr,
aaddr);
*/
return EXC_None;
}
void interp_mem() {
mem_wb.reg_write = ex_mem.reg_write;
mem_wb.rt = ex_mem.rt;
mem_wb.alu_res = ex_mem.alu_res;
mem_wb.mem_to_reg = ex_mem.mem_to_reg;
mem_wb.reg_dst = ex_mem.reg_dst;
if (ex_mem.mem_read) {
mem_wb.read_data = GET_BIGWORD(mem, ex_mem.alu_res);
}
if (ex_mem.mem_write) {
SET_BIGWORD(mem, ex_mem.alu_res, ex_mem.rt_value);
}
}
