extern void stx5206_usb_init(void)
{
unsigned long sysconf;
/* USB_HOST_SOFT_RESET: active low usb host sof reset */
// sc = sysconf_claim(SYS_CFG, 4, 1, 1, "USB");
// sysconf_write(sc, 1);
sysconf = readl(STX5206_SYSCONF_SYS_CFG04);
SET_SYSCONF_BIT(sysconf, 1, 1);
writel(sysconf, STX5206_SYSCONF_SYS_CFG04);
/* suspend_from_config: Signal to suspend USB PHY */
// sc = sysconf_claim(SYS_CFG, 10, 5, 5, "USB");
// sysconf_write(sc, 0);
sysconf = readl(STX5206_SYSCONF_SYS_CFG10);
SET_SYSCONF_BIT(sysconf, 0, 5);
writel(sysconf, STX5206_SYSCONF_SYS_CFG10);
/* usb_power_down_req: power down request for USB Host module */
// sc = sysconf_claim(SYS_CFG, 32, 4, 4, "USB");
// sysconf_write(sc, 0);
sysconf = readl(STX5206_SYSCONF_SYS_CFG32);
SET_SYSCONF_BIT(sysconf, 0, 4);
writel(sysconf, STX5206_SYSCONF_SYS_CFG32);
/* start the USB Wrapper Host Controller */
ST40_start_host_control(
USB_FLAGS_STRAP_8BIT |
USB_FLAGS_STBUS_CONFIG_THRESHOLD128);
}
void stx7108_pioalt_pad(int port, const int pin,
const struct stx7108_pioalt_pad_cfg * const cfg)
{
int num, bit;
unsigned long sysconf, *sysconfReg;
#if 0
printf("%s(port=%d, pin=%d, oe=%d, pu=%d, od=%d)\n", __func__, port, pin, cfg->oe, cfg->pu, cfg->od);
BUG_ON(pin < 0 || pin > 7);
BUG_ON(!cfg);
#endif
switch (port)
{
case 0 ... 14:
num = 15 + (port / 4); /* in Bank #2 */
sysconfReg = (unsigned long*)STX7108_BANK2_SYSGFG(num);
break;
case 15 ... 26:
port -= 15;
num = 12 + (port / 4); /* in Bank #4 */
sysconfReg = (unsigned long*)STX7108_BANK4_SYSGFG(num);
break;
default:
BUG();
return;
}
bit = ((port * 8) + pin) % 32;
/* set the "Output Enable" pad control */
if (cfg->oe >= 0)
{
sysconf = readl(sysconfReg);
SET_SYSCONF_BIT(sysconf, cfg->oe, bit);
writel(sysconf, sysconfReg);
}
sysconfReg += 4; /* skip 4 syscfg registers */
/* set the "Pull Up" pad control */
if (cfg->pu >= 0)
{
sysconf = readl(sysconfReg);
SET_SYSCONF_BIT(sysconf, cfg->pu, bit);
writel(sysconf, sysconfReg);
}
sysconfReg += 4; /* skip another 4 syscfg registers */
/* set the "Open Drain Enable" pad control */
if (cfg->od >= 0)
{
sysconf = readl(sysconfReg);
SET_SYSCONF_BIT(sysconf, cfg->od, bit);
writel(sysconf, sysconfReg);
}
}
extern void fli7510_usb_init(const enum fli7510_usb_ovrcur_mode ovrcur_mode)
{
unsigned long sysconf;
switch (ovrcur_mode) {
case fli7510_usb_ovrcur_disabled:
/* CONFIG_SYS_COMMS_CONFIG_1[12] = usba_enable_pad_override */
sysconf = readl(CONFIG_SYS_COMMS_CONFIG_1);
SET_SYSCONF_BIT(sysconf, 1, USBA_ENABLE_PAD_OVERRIDE);
writel(sysconf, CONFIG_SYS_COMMS_CONFIG_1);
/* CONFIG_SYS_COMMS_CONFIG_1[13] = usba_ovrcur */
sysconf = readl(CONFIG_SYS_COMMS_CONFIG_1);
SET_SYSCONF_BIT(sysconf, 1, USBA_OVRCUR);
writel(sysconf, CONFIG_SYS_COMMS_CONFIG_1);
break;
default:
/* CONFIG_SYS_COMMS_CONFIG_1[12] = usba_enable_pad_override */
sysconf = readl(CONFIG_SYS_COMMS_CONFIG_1);
SET_SYSCONF_BIT(sysconf, 0, USBA_ENABLE_PAD_OVERRIDE);
writel(sysconf, CONFIG_SYS_COMMS_CONFIG_1);
/* CONFIG_SYS_COMMS_CONFIG_1[11] = usba_ovrcur_polarity */
switch (ovrcur_mode) {
case fli7510_usb_ovrcur_active_high:
sysconf = readl(CONFIG_SYS_COMMS_CONFIG_1);
SET_SYSCONF_BIT(sysconf, 0, USBA_OVRCUR_POLARITY);
writel(sysconf, CONFIG_SYS_COMMS_CONFIG_1);
break;
case fli7510_usb_ovrcur_active_low:
sysconf = readl(CONFIG_SYS_COMMS_CONFIG_1);
SET_SYSCONF_BIT(sysconf, 1, USBA_OVRCUR_POLARITY);
writel(sysconf, CONFIG_SYS_COMMS_CONFIG_1);
break;
default:
BUG();
break;
}
break;
}
/* now route the PIOs corectly */
SET_PIO_PIN(ST40_PIO_BASE(27), 1, STPIO_IN); /* USB_A_OVRCUR */
SET_PIO_PIN(ST40_PIO_BASE(27), 2, STPIO_ALT_OUT); /* USB_A_PWREN */
/* start the USB Wrapper Host Controller */
ST40_start_host_control(
USB_FLAGS_STRAP_16BIT |
USB_FLAGS_STRAP_PLL |
USB_FLAGS_STBUS_CONFIG_THRESHOLD256);
}
extern void stmac_set_mac_speed(int speed)
{
unsigned long sysconf;
/* gmac_mac_speed = speed==100 ? 1 : 0 */
sysconf = readl(STX5206_SYSCONF_SYS_CFG07);
SET_SYSCONF_BIT(sysconf, speed==100, MAC_SPEED_SEL);
writel(sysconf, STX5206_SYSCONF_SYS_CFG07);
}
extern void stmac_set_mac_speed(const int speed)
{
unsigned long sysconf;
/* CONFIG_SYS_COMMS_CONFIG_2[25] = gmac_mac_speed */
/* gmac_mac_speed = speed==100 ? 1 : 0 */
sysconf = readl(CONFIG_SYS_COMMS_CONFIG_2);
SET_SYSCONF_BIT(sysconf, speed==100, GMAC_MAC_SPEED);
writel(sysconf, CONFIG_SYS_COMMS_CONFIG_2);
}
extern void stmac_set_mac_speed(const int speed)
{
unsigned long sysconf;
sysconf = *STX5197_HD_CONF_MON_CONFIG_CONTROL_E;
/* MAC speed*/
/* CFG_CTRL_E.MAC_SPEED_SEL = speed==100 ? 1 : 0 [1] */
SET_SYSCONF_BIT(sysconf, speed==100, 1);
*STX5197_HD_CONF_MON_CONFIG_CONTROL_E = sysconf;
}
/* ETH MAC pad configuration */
static void stmac_eth_hw_setup(const int rmii, const int ext_clk, const int phy_bus)
{
unsigned long sysconf;
sysconf = *STX5197_HD_CONF_MON_CONFIG_CONTROL_E;
/* Ethernet interface on */
/* CFG_CTRL_E.ETHERNET_INTERFACE_ON = 1 [0] */
SET_SYSCONF_BIT(sysconf, 1, 0);
/* MII plyclk out enable: 0=output, 1=input */
/* CFG_CTRL_E.MII_PHYCLK_OUT_EN = ext_clk ? 1 : 0 [6] */
SET_SYSCONF_BIT(sysconf, ext_clk, 6);
/* RMII/MII pin mode */
/* CFG_CTRL_E.MII_ETHERNET_SEL = rmii ? 2 : 3 [8:7] */
SET_SYSCONF_BITS(sysconf, rmii, 7, 8, 0x2, 0x3);
/* MII mode */
/* CFG_CTRL_E.MII_MODE = rmii ? 0 : 1 [2] */
SET_SYSCONF_BIT(sysconf, !rmii, 2);
*STX5197_HD_CONF_MON_CONFIG_CONTROL_E = sysconf;
}
extern void stmac_set_mac_speed(int speed)
{
#if CFG_STM_STMAC_BASE == CFG_STM_STMAC0_BASE /* MII0 */
unsigned long * const sysconfReg = (void*)STX7108_MII_SYSGFG(27);
#elif CFG_STM_STMAC_BASE == CFG_STM_STMAC1_BASE /* MII1 */
unsigned long * const sysconfReg = (void*)STX7108_MII_SYSGFG(23);
#else
#error Unknown base address for the STM GMAC
#endif
unsigned long sysconf = *sysconfReg;
/* MIIx_MAC_SPEED_SEL = 0|1 */
SET_SYSCONF_BIT(sysconf, (speed==100), MAC_SPEED_SEL);
*sysconfReg = sysconf;
}
/*
* ETH GMAC PIO configuration
*/
extern void fli7540_configure_ethernet(
const enum fli7540_ethernet_mode mode,
const int ext_clk,
const int phy_bus)
{
struct fli7540_gmac_pin *pins;
int pins_num;
unsigned char phy_sel, enmii;
int i;
unsigned long sysconf;
/* Ethernet interface on */
/* CONFIG_SYS_COMMS_CONFIG_2[24] = gmac_enable */
sysconf = readl(CONFIG_SYS_COMMS_CONFIG_2);
SET_SYSCONF_BIT(sysconf, 1, GMAC_ENABLE);
writel(sysconf, CONFIG_SYS_COMMS_CONFIG_2);
switch (mode) {
case fli7540_ethernet_mii:
phy_sel = 0;
enmii = 1;
pins = fli7540_gmac_mii_pins;
pins_num = ARRAY_SIZE(fli7540_gmac_mii_pins);
break;
case fli7540_ethernet_rmii:
phy_sel = 4;
enmii = 1;
pins = fli7540_gmac_rmii_pins;
pins_num = ARRAY_SIZE(fli7540_gmac_rmii_pins);
break;
case fli7540_ethernet_gmii:
phy_sel = 0;
enmii = 1;
pins = fli7540_gmac_gmii_pins;
pins_num = ARRAY_SIZE(fli7540_gmac_gmii_pins);
/* CONFIG_SYS_COMMS_CONFIG_1[18:17] = conf_pio24_alternate */
sysconf = readl(CONFIG_SYS_COMMS_CONFIG_1);
sysconf &= ~(0x3ul<<CONF_PIO24_ALTERNATE);
sysconf |= (0x2ul<<CONF_PIO24_ALTERNATE);
writel(sysconf, CONFIG_SYS_COMMS_CONFIG_1);
break;
case fli7540_ethernet_reverse_mii:
phy_sel = 0;
enmii = 0;
pins = fli7540_gmac_reverse_mii_pins;
pins_num = ARRAY_SIZE(fli7540_gmac_reverse_mii_pins);
break;
default:
BUG();
return;
}
/* CONFIG_SYS_COMMS_CONFIG_2[28:26] = phy_intf_sel */
sysconf = readl(CONFIG_SYS_COMMS_CONFIG_2);
sysconf &= ~(0x7ul<<PHY_INTF_SEL);
sysconf |= (phy_sel<<PHY_INTF_SEL);
// writel(sysconf, CONFIG_SYS_COMMS_CONFIG_2);
/* CONFIG_SYS_COMMS_CONFIG_2[8] = gmac_mii_enable */
// sysconf = readl(CONFIG_SYS_COMMS_CONFIG_2);
SET_SYSCONF_BIT(sysconf, enmii, GMAC_MII_ENABLE);
// writel(sysconf, CONFIG_SYS_COMMS_CONFIG_2);
/* CONFIG_SYS_COMMS_CONFIG_2[9] = gmac_phy_clock_sel */
// sysconf = readl(CONFIG_SYS_COMMS_CONFIG_2);
SET_SYSCONF_BIT(sysconf, ext_clk, GMAC_PHY_CLOCK_SEL);
writel(sysconf, CONFIG_SYS_COMMS_CONFIG_2);
/* choose the correct direction for PHYCLK */
pins[0].dir = (ext_clk) ? STPIO_IN : STPIO_ALT_OUT;
/* set all the PIOs correctly */
for (i = 0; i < pins_num; i++)
{
SET_PIO_PIN(ST40_PIO_BASE(pins[i].port), pins[i].pin, pins[i].dir);
}
}
/*
* ETH GMAC PIO configuration
*/
extern void stx5206_configure_ethernet(
const enum stx5206_ethernet_mode mode,
const int ext_clk,
const int phy_bus)
{
unsigned int phy_sel, enmii;
unsigned long phy_clk_rate;
unsigned long sysconf;
switch (mode) {
case stx5206_ethernet_mii:
phy_sel = 0x0;
enmii = 1;
phy_clk_rate = 25000000; /* 25 MHz */
break;
case stx5206_ethernet_rmii:
phy_sel = 0x4;
enmii = 1;
phy_clk_rate = 50000000; /* 50 MHz */
break;
case stx5206_ethernet_reverse_mii:
phy_sel = 0x0;
enmii = 0;
phy_clk_rate = 25000000; /* 25 MHz */
break;
default:
BUG();
return;
}
/* ethernet_interface_on */
sysconf = readl(STX5206_SYSCONF_SYS_CFG07);
SET_SYSCONF_BIT(sysconf, 1, ETHERNET_INTERFACE_ON);
writel(sysconf, STX5206_SYSCONF_SYS_CFG07);
/* phy_clk_ext: MII_PHYCLK pad function: 1 = phy clock is external,
* 0 = phy clock is provided by STx5289 */
sysconf = readl(STX5206_SYSCONF_SYS_CFG07);
SET_SYSCONF_BIT(sysconf, ext_clk, PHY_CLK_EXT);
writel(sysconf, STX5206_SYSCONF_SYS_CFG07);
/* phy_intf_sel */
sysconf = readl(STX5206_SYSCONF_SYS_CFG07);
SET_SYSCONF_BITS(sysconf, 1, 24, 26, phy_sel, phy_sel);
writel(sysconf, STX5206_SYSCONF_SYS_CFG07);
/* enMii: 1 = MII mode, 0 = Reverse MII mode */
sysconf = readl(STX5206_SYSCONF_SYS_CFG07);
SET_SYSCONF_BIT(sysconf, enmii, ENMII);
writel(sysconf, STX5206_SYSCONF_SYS_CFG07);
/* Set PHY clock frequency (if used) */
if (!ext_clk)
{
if (phy_clk_rate == 25000000) /* 25 MHz */
{
/* CLKGENA.CLK_DIV_LS[13] = CLK_ETHERNET_PHY = 25 MHz */
writel(17, STX5206_CLOCKGENA_PLL0LS_DIV13_CFG);
}
#if 0 /* QQQ: Need to check this! */
else /* 50 MHz */
{
/* CLKGENA.CLK_DIV_LS[13] = CLK_ETHERNET_PHY = 50 MHz */
writel(8, STX5206_CLOCKGENA_PLL0LS_DIV13_CFG);
}
#endif
}
}
/* ETH MAC pad configuration */
extern void stx7108_configure_ethernet(
const int port,
const struct stx7108_ethernet_config * const config)
{
unsigned long sysconf;
int sc_regnum;
struct stx7108_gmac_pin *pins;
int pins_num;
unsigned char phy_sel, enmii;
int i;
switch (port) {
case 0:
sc_regnum = 27;
/* ENABLE_GMAC0 */
sysconf = *STX7108_MII_SYSGFG(53);
SET_SYSCONF_BIT(sysconf, TRUE, ENABLE_GMAC);
*STX7108_MII_SYSGFG(53) = sysconf;
break;
case 1:
sc_regnum = 23;
/* ENABLE_GMAC1 */
sysconf = *STX7108_MII_SYSGFG(67);
SET_SYSCONF_BIT(sysconf, TRUE, ENABLE_GMAC);
*STX7108_MII_SYSGFG(67) = sysconf;
break;
default:
BUG();
return;
};
switch (config->mode) {
case stx7108_ethernet_mode_mii:
phy_sel = 0;
enmii = 1;
pins = stx7108_gmac_mii_pins;
pins_num = ARRAY_SIZE(stx7108_gmac_mii_pins);
break;
case stx7108_ethernet_mode_rmii:
phy_sel = 4;
enmii = 1;
pins = stx7108_gmac_rmii_pins;
pins_num = ARRAY_SIZE(stx7108_gmac_rmii_pins);
break;
case stx7108_ethernet_mode_gmii:
phy_sel = 0;
enmii = 1;
pins = stx7108_gmac_gmii_pins;
pins_num = ARRAY_SIZE(stx7108_gmac_gmii_pins);
break;
case stx7108_ethernet_mode_gmii_gtx:
phy_sel = 0;
enmii = 1;
pins = stx7108_gmac_gmii_gtx_pins;
pins_num = ARRAY_SIZE(stx7108_gmac_gmii_gtx_pins);
break;
case stx7108_ethernet_mode_reverse_mii:
phy_sel = 0;
enmii = 0;
pins = stx7108_gmac_reverse_mii_pins;
pins_num = ARRAY_SIZE(stx7108_gmac_reverse_mii_pins);
break;
default:
BUG();
return;
}
/* MIIx_PHY_SEL */
sysconf = *STX7108_MII_SYSGFG(sc_regnum);
SET_SYSCONF_BITS(sysconf, TRUE, 2,4, phy_sel,phy_sel);
*STX7108_MII_SYSGFG(sc_regnum) = sysconf;
/* ENMIIx */
sysconf = *STX7108_MII_SYSGFG(sc_regnum);
SET_SYSCONF_BIT(sysconf, enmii, ENMII);
*STX7108_MII_SYSGFG(sc_regnum) = sysconf;
pins[0].dir = config->ext_clk ? IN : OUT;
for (i = 0; i < pins_num; i++) {
const struct stx7108_gmac_pin *pin = &pins[i];
int portno = pin->pio[port].port;
int pinno = pin->pio[port].pin;
struct stx7108_pioalt_retime_cfg retime_cfg = {
-1, -1, -1, -1, -1, -1 /* -1 means "do not set */
};
stx7108_pioalt_select(portno, pinno, pin->pio[port].alt);
stx7108_pioalt_pad(portno, pinno, pin->dir);
switch (pin->type) {
case BYPASS:
retime_cfg.clknotdata = 0;
retime_cfg.retime = 0;
break;
case CLOCK:
retime_cfg.clknotdata = 1;
retime_cfg.clk1notclk0 = port;
break;
case PHY_CLOCK:
retime_cfg.clknotdata = 1;
if (config->mode == stx7108_ethernet_mode_gmii_gtx) {
retime_cfg.clk1notclk0 = 1;
retime_cfg.double_edge = 0;
} else {
retime_cfg.clk1notclk0 = 0;
}
break;
case DGTX: /* extra configuration for GMII (GTK CLK) */
if (port == 1) {
retime_cfg.retime = 1;
retime_cfg.clk1notclk0 = 1;
retime_cfg.double_edge = 0;
retime_cfg.clknotdata = 0;
} else {
retime_cfg.retime = 1;
retime_cfg.clk1notclk0 = 0;
retime_cfg.double_edge = 0;
retime_cfg.clknotdata = 0;
}
break;
case DATA:
retime_cfg.clknotdata = 0;
retime_cfg.retime = 1;
retime_cfg.clk1notclk0 = port;
break;
default:
BUG();
break;
}
stx7108_pioalt_retime(portno, pinno, &retime_cfg);
}
}
static void stx7108_pioalt_retime(const int port, const int pin,
const struct stx7108_pioalt_retime_cfg * const cfg)
{
int num;
unsigned long sysconf, *sysconfReg;
#if 0
printf("%s(port=%d, pin=%d, retime=%d, clk1notclk0=%d, "
"clknotdata=%d, double_edge=%d, invertclk=%d, "
"delay_input=%d)\n", __func__, port, pin,
cfg->retime, cfg->clk1notclk0, cfg->clknotdata,
cfg->double_edge, cfg->invertclk, cfg->delay_input
);
BUG_ON(pin < 0 || pin > 7);
#endif
switch (port)
{
case 0 ... 14:
switch (port)
{
case 1:
num = 32;
break;
case 6 ... 14:
num = 34 + ((port - 6) * 2);
break;
default:
BUG();
return;
}
sysconfReg = (unsigned long*)STX7108_BANK2_SYSGFG(num);
break;
case 15 ... 23:
num = 48 + ((port - 15) * 2);
sysconfReg = (unsigned long*)STX7108_BANK4_SYSGFG(num);
break;
default:
BUG();
return;
}
sysconfReg += 0; /* use retime configuration register #0 */
if (cfg->clk1notclk0 >= 0)
{
sysconf = readl(sysconfReg);
SET_SYSCONF_BIT(sysconf, cfg->clk1notclk0, 0 + pin);
writel(sysconf, sysconfReg);
}
if (cfg->clknotdata >= 0)
{
sysconf = readl(sysconfReg);
SET_SYSCONF_BIT(sysconf, cfg->clknotdata, 8 + pin);
writel(sysconf, sysconfReg);
}
if (cfg->delay_input >= 0)
{
sysconf = readl(sysconfReg);
SET_SYSCONF_BIT(sysconf, cfg->delay_input, 16 + pin);
writel(sysconf, sysconfReg);
}
if (cfg->double_edge >= 0)
{
sysconf = readl(sysconfReg);
SET_SYSCONF_BIT(sysconf, cfg->double_edge, 24+ pin);
writel(sysconf, sysconfReg);
}
sysconfReg += 1; /* use retime configuration register #1 */
if (cfg->invertclk >= 0)
{
sysconf = readl(sysconfReg);
SET_SYSCONF_BIT(sysconf, cfg->invertclk, 0 + pin);
writel(sysconf, sysconfReg);
}
if (cfg->retime >= 0)
{
sysconf = readl(sysconfReg);
SET_SYSCONF_BIT(sysconf, cfg->retime, 8 + pin);
writel(sysconf, sysconfReg);
}
}
extern void fli7540_usb_init(
const int port,
const enum fli7540_usb_ovrcur_mode ovrcur_mode)
{
static int xtal_initialized;
int clken, rstn;
int override, ovrcur, polarity;
unsigned long sysconf;
if (!xtal_initialized++)
{
sysconf = readl(CONFIG_SYS_SPARE_1);
#if defined(CONFIG_ST40_FLI7510)
SET_SYSCONF_BIT(sysconf, 0, USB_XTAL_VALID);
#else
SET_SYSCONF_BIT(sysconf, 1, USB_XTAL_VALID);
#endif /* CONFIG_ST40_FLI7510 */
writel(sysconf, CONFIG_SYS_SPARE_1);
}
switch (port) {
case 0:
clken = 21;
rstn = 23;
override = 12;
ovrcur = 13;
polarity = 11;
#if defined(CONFIG_ST40_FLI7510)
SET_PIO_PIN(ST40_PIO_BASE(27), 1, STPIO_IN); /* USB_A_OVRCUR */
SET_PIO_PIN(ST40_PIO_BASE(27), 2, STPIO_ALT_OUT); /* USB_A_PWREN */
#else
SET_PIO_PIN(ST40_PIO_BASE(26), 3, STPIO_IN); /* USB_A_OVRCUR */
SET_PIO_PIN(ST40_PIO_BASE(26), 4, STPIO_ALT_OUT); /* USB_A_PWREN */
#endif /* CONFIG_ST40_FLI7510 */
break;
case 1:
clken = 22;
rstn = 24;
override = 15;
