static int ar7646_read12_ser(struct device *dev, unsigned command)
{
struct spi_device *spi = to_spi_device(dev);
struct ar7646 *ts = dev_get_drvdata(dev);
struct ser_req *req = kzalloc(sizeof *req, GFP_KERNEL);
int status;
int use_internal;
u8 tx_buf[3][2],rx_buf[2];
if (!req)
return -ENOMEM;
spi_message_init(&req->msg);
//req->command <<= 1;
tx_buf[0][0] = 0x01;
tx_buf[0][1] = (u8)((u16)0xd7 << 1);
//tx_buf[0][0] = 0xd7;
req->xfer[0].tx_buf = tx_buf[0];
req->xfer[0].len = SET_TX_RX_LEN(2, 2);
req->xfer[0].rx_buf = rx_buf;//tt
spi_message_add_tail(&req->xfer[0], &req->msg);
req->command = (u8) command;
tx_buf[1][0] = 0x01;
tx_buf[1][1] = command << 1;
req->xfer[1].tx_buf = tx_buf[1];
//req->xfer[0].tx_buf = &req->command;
req->xfer[1].len = SET_TX_RX_LEN(2, 2);
req->xfer[1].rx_buf = &req->sample;//tt
spi_message_add_tail(&req->xfer[1], &req->msg);
tx_buf[2][0] = 0x01;
tx_buf[2][1] = 0xe0 << 1;
//tx_buf[2][0] = 0xe0;
req->xfer[2].tx_buf = tx_buf[2];
//req->xfer[0].tx_buf = &req->command;
req->xfer[2].len = SET_TX_RX_LEN(2, 2);
req->xfer[2].rx_buf = rx_buf;//tt
spi_message_add_tail(&req->xfer[2], &req->msg);
// ts->irq_disabled = 1;
disable_irq(spi->irq);
status = spi_sync(spi, &req->msg);
// ts->irq_disabled = 0;
enable_irq(spi->irq);
/* on-wire is a must-ignore bit, a BE12 value, then padding */
status = be16_to_cpu(req->sample);
status = status >> 4;
status &= 0x0fff;
DEBUG("--tx=0x%4x rx =0x%4x -> 0x%4x\n",command,req->sample,status);
kfree(req);
return status;
}
static int ar7646_write_data(struct ts_ar7646 *touchscreen, u16 page, u16 addr, u16 data)
{
int err = 0;
struct spi_message msg;
struct spi_transfer xfer;
u16 tx_buf[2] = {0};
DEBUG("tsc2000_write_data \n");
dev_dbg(&touchscreen->spi->dev, "tsc2000_write_data()\n");
tx_buf[0] = WRITE_CMD & ((addr<<ADDR_OFFSET) | page);
tx_buf[1] = data;
//spi_setup(touchscreen->spi); //20080417 JS mask
spi_message_init(&msg);
memset(&xfer, 0, sizeof(struct spi_transfer));
// xfer.speed_hz = 300;
xfer.tx_buf = tx_buf;
// xfer.rx_buf = &stat;
xfer.len = SET_TX_RX_LEN(2, 0);
// xfer.len = 2;
spi_message_add_tail(&xfer, &msg);
err = spi_sync(touchscreen->spi, &msg);
DEBUG("tsc2000_write_data err=%d\n",err);
return err;
}
static int
socle_spi_at25040_set_write_enable(void)
{
u8 cmd;
cmd = AT25040_CMD_WREN;
if (socle_spi_transfer(&cmd, NULL,SET_TX_RX_LEN(1, 0)))
return -1;
return 0;
}
static int
socle_spi_at25040_read_data(u8 addr, u8 *buf, u16 len)
{
u8 cmd[2] = {0};
cmd[0] = AT25040_CMD_READ;
cmd[1] = addr;
if (socle_spi_transfer(cmd, buf, SET_TX_RX_LEN(2,len)))
return -1;
return 0;
}
static int
socle_spi_at25040_page_write_data(u8 addr, u8 *buf)
{
u8 tx_buf[10] = {0};
if (socle_spi_at25040_set_write_enable())
return -1;
if (socle_spi_at25040_wait_for_write_enable())
return -1;
tx_buf[0] = AT25040_CMD_WRITE;
tx_buf[1] = addr;
memcpy((char *)&tx_buf[2], (char *)buf, AT25040_MAX_PKG_LEN);
if(socle_spi_transfer(tx_buf, NULL, SET_TX_RX_LEN(AT25040_MAX_PKG_LEN+2,0)))
return -1;
/* Wait for the device to be ready */
if (socle_spi_at25040_wait_for_ready())
return -1;
return 0;
}
static int
socle_spi_at25040_wait_for_ready(void)
{
u8 cmd, stat;
u32 retry_cnt = 0;
cmd = AT25040_CMD_RDSR;
while (1) {
if (socle_spi_transfer(&cmd, &stat, SET_TX_RX_LEN(1, 1)))
return -1;
if (!(stat & AT25040_STAT_RDY))
break;
if (retry_cnt > RETRY_CNT_THRESHOLD) {
printf("Retry count (%d) exceed threshold\n", retry_cnt);
return -1;
}
retry_cnt++;
}
return 0;
}
static ssize_t sq_spi_download_write(struct file *file, const char __user *data,
size_t len, loff_t *ppos)
{
int err = 0;
//char *p;
struct spi_message msg;
struct spi_transfer xfer;
//char buf[128];
char *buf;
buf = kmalloc(len,GFP_KERNEL);
if(!buf) {
return -ENOMEM;
}
if(copy_from_user(buf,data,len)) {
return -EFAULT;
}
SPI_DOWNLOAD_DBG(" write len=0x%x =>",len);
#if (SPI_CTRL_GPIO_EN == 1 )
do {
#endif
/*
i=0;
while(1) {
sq_gpio_set_low(TST_GPIO_G,1<<i);
sq_gpio_set_high(TST_GPIO_G,1<<i);
i++;
if(i>0x07)
i=0;
}
*/
#if 0
i=1;
while(i--)
{
sq_gpio_set_low(TST_GPIO_G,DL_PROGB);
udelay(20);
sq_gpio_set_high(TST_GPIO_G,DL_PROGB);
/*
sq_gpio_set_low(TST_GPIO_G,DL_RST);
udelay(20);
sq_gpio_set_high(TST_GPIO_G,DL_RST);
sq_gpio_set_low(TST_GPIO_G,DL_INITB);
udelay(20);
sq_gpio_set_high(TST_GPIO_G,DL_INITB);
sq_gpio_set_low(TST_GPIO_G,DL_DONE);
udelay(20);
sq_gpio_set_high(TST_GPIO_G,DL_DONE);
*/
//sq_gpio_in(TST_GPIO_G,DL_INITB);
//sq_gpio_in(TST_GPIO_G,DL_DONE);
//sq_spi_download_write_rst();
}
#endif
/*
c = len;
p = data;
while(c--) {
printk("%c",*p++);
}
printk("\n");
*/
#if 1
spi_message_init(&msg);
memset(&xfer, 0, sizeof(struct spi_transfer));
//SPI_DOWNLOAD_DBG(" bits_per_word= %d",msg.spi->bits_per_word);
xfer.tx_buf = buf;
// xfer.tx_buf = tx_buf;
xfer.len = SET_TX_RX_LEN(len, 0);
spi_message_add_tail(&xfer, &msg);
#if (SPI_CTRL_GPIO_EN == 1 )
sq_spi_download_write_before();
#endif
err = spi_sync(sq_spi_download_device, &msg);
#if (SPI_CTRL_GPIO_EN == 1 )
//sq_spi_download_write_chk();
} while (sq_spi_download_write_chk() != 0 );
#endif
#endif
kfree(buf);
// SPI_DOWNLOAD_DBG(" <============== sq_spi_download_write end ===============>");
return 0;
}
static int ar7646_read_data(struct device *dev, u16 *x, u16 *y, u16 *z1, u16 *z2)
{
struct spi_device *spi = to_spi_device(dev);
struct ar7646 *ts = dev_get_drvdata(dev);
struct ser_req *req = kzalloc(sizeof *req, GFP_KERNEL);
int status;
int use_internal;
u8 tx_buf[6][2],c = 0;
u16 rx_buf[6];
if (!req)
return -ENOMEM;
spi_message_init(&req->msg);
tx_buf[c][0] = 0x01;
tx_buf[c][1] = (u8)((u16)0xd7 << 1);
req->xfer[c].tx_buf = tx_buf[c];
req->xfer[c].len = SET_TX_RX_LEN(2, 2);
req->xfer[c].rx_buf = &rx_buf[c];//tt
spi_message_add_tail(&req->xfer[c], &req->msg);
c++;
tx_buf[c][0] = 0x01;
tx_buf[c][1] = ((READ_12BIT_VREF(d_x)| AR_PD10_ALL_ON) << 1);
req->xfer[c].tx_buf = tx_buf[c];
req->xfer[c].len = SET_TX_RX_LEN(2, 2);
req->xfer[c].rx_buf = &rx_buf[c];//tt
spi_message_add_tail(&req->xfer[c], &req->msg);
c++;
tx_buf[c][0] = 0x01;
tx_buf[c][1] = ((READ_12BIT_VREF(d_y)| AR_PD10_ALL_ON) << 1);
req->xfer[c].tx_buf = tx_buf[c];
req->xfer[c].len = SET_TX_RX_LEN(2, 2);
req->xfer[c].rx_buf = &rx_buf[c];//tt
spi_message_add_tail(&req->xfer[c], &req->msg);
c++;
tx_buf[c][0] = 0x01;
tx_buf[c][1] = ((READ_12BIT_VREF(d_z1)| AR_PD10_ALL_ON) << 1);
req->xfer[c].tx_buf = tx_buf[c];
req->xfer[c].len = SET_TX_RX_LEN(2, 2);
req->xfer[c].rx_buf = &rx_buf[c];//tt
spi_message_add_tail(&req->xfer[c], &req->msg);
c++;
tx_buf[c][0] = 0x01;
tx_buf[c][1] = ((READ_12BIT_VREF(d_z2)| AR_PD10_ALL_ON) << 1);
req->xfer[c].tx_buf = tx_buf[c];
req->xfer[c].len = SET_TX_RX_LEN(2, 2);
req->xfer[c].rx_buf = &rx_buf[c];//tt
spi_message_add_tail(&req->xfer[c], &req->msg);
c++;
tx_buf[c][0] = 0x01;
tx_buf[c][1] = 0xe0 << 1;
req->xfer[c].tx_buf = tx_buf[c];
req->xfer[c].len = SET_TX_RX_LEN(2, 2);
req->xfer[c].rx_buf = &rx_buf[c];//tt
spi_message_add_tail(&req->xfer[c], &req->msg);
// ts->irq_disabled = 1;
disable_irq(spi->irq);
status = spi_sync(spi, &req->msg);
// ts->irq_disabled = 0;
enable_irq(spi->irq);
/* on-wire is a must-ignore bit, a BE12 value, then padding */
rx_buf[1] = be16_to_cpu(rx_buf[1]);
*x = rx_buf[1] >> 4;
*x &= 0x0fff;
rx_buf[2] = be16_to_cpu(rx_buf[2]);
*y = rx_buf[2] >> 4;
*y &= 0x0fff;
rx_buf[3] = be16_to_cpu(rx_buf[3]);
*z1 = rx_buf[3] >> 4;
*z1 &= 0x0fff;
rx_buf[4] = be16_to_cpu(rx_buf[4]);
*z2 = rx_buf[4] >> 4;
*z2 &= 0x0fff;
// DEBUG("--tx=0x%4x rx =0x%4x -> 0x%4x\n",command,req->sample,status);
kfree(req);
return status;
}
extern int
sq_spi_internal_normal_run(int autotest)
{
/* Reset SPI controller */
sq_spi_write(
sq_spi_read(SQ_SPI_FWCR) |
SQ_SPI_SOFT_RST,
SQ_SPI_FWCR);
/* Configure SPI controller */
sq_spi_write(
#ifdef CONFIG_SQ8000
SQ_SPI_MASTER_SIGNAL_CTL_HW |
SQ_SPI_MASTER_SIGNAL_ACT_NO |
SQ_SPI_MODE_MASTER |
#endif
SQ_SPI_SOFT_N_RST |
SQ_SPI_TXRX_N_RUN |
SQ_SPI_CLK_IDLE_AST |
SQ_SPI_TXRX_SIMULT_DIS |
SQ_SPI_CPOL_0 |
SQ_SPI_CPHA_0 |
SQ_SPI_TX_LSB_FIRST |
SQ_SPI_OP_LOOPBACK,
SQ_SPI_FWCR);
/* Enable SPI interrupt */
sq_spi_write(
//SQ_SPI_IER_RXFIFO_OVR_INT_EN |
//SQ_SPI_IER_TXFIFO_INT_EN |
SQ_SPI_IER_RXFIFO_INT_EN |
SQ_SPI_IER_RX_COMPLETE_INT_EN,
SQ_SPI_IER);
/* Configure FIFO and clear Tx & Rx FIFO */
sq_spi_write(
SQ_SPI_RXFIFO_INT_TRIGGER_LEVEL_4 |
SQ_SPI_TXFIFO_INT_TRIGGER_LEVEL_4 |
SQ_SPI_RXFIFO_CLR |
SQ_SPI_TXFIFO_CLR,
SQ_SPI_FCR);
/* Set the SPI slaves select and characteristic control register */
sq_spi_write(
SQ_SPI_CHAR_LEN_8 |
SQ_SPI_SLAVE_SEL_0 |
SQ_SPI_CLK_DIV(LOOKBACK_DIV),
SQ_SPI_SSCR);
/* Config SPI clock delay */
sq_spi_write(
SQ_SPI_PBTXRX_DELAY_NONE |
SQ_SPI_PBCT_DELAY_NONE |
SQ_SPI_PBCA_DELAY_1_2,
SQ_SPI_DLYCR);
/* Set per char length */
sq_spi_set_current_mode(MODE_CHAR_LEN_8);
/* Clear pattern buffer and compare buffer */
memset(sq_spi_pattern_buf, 0x0, PATTERN_BUF_SIZE);
memset(sq_spi_cmpr_buf, 0x0, PATTERN_BUF_SIZE);
/* Make test pattern */
sq_spi_make_test_pattern(sq_spi_pattern_buf, PATTERN_BUF_SIZE);
if (sq_spi_transfer(sq_spi_pattern_buf, sq_spi_cmpr_buf, SET_TX_RX_LEN(PATTERN_BUF_SIZE, PATTERN_BUF_SIZE)))
return -1;
return sq_spi_compare_memory(sq_spi_pattern_buf, sq_spi_cmpr_buf, PATTERN_BUF_SIZE, autotest);
}
