// PUT REGISTER
Value *
arch_put_reg(cpu_t *cpu, uint32_t index, Value *v, uint32_t bits, bool sext,
BasicBlock *bb)
{
Value **regs = cpu->ptr_gpr;
uint32_t size = cpu->info.register_size[CPU_REG_GPR];
uint32_t count = cpu->info.register_count[CPU_REG_GPR];
/*
* XXX If the index is past the number of the available GPRs,
* then it's considered an XR. This is in order to maintain
* compatibility with the current implementation.
*/
if (index >= count) {
index -= count;
regs = cpu->ptr_xr;
size = cpu->info.register_size[CPU_REG_XR];
count = cpu->info.register_count[CPU_REG_XR];
if (index >= count) {
assert(0 && "GPR/XR register index is out of range!");
return NULL;
}
}
/*
* if the caller cares about bit size and
* the size is not the register size, we'll zext or sext
*/
if (bits != 0 && size != bits) {
if (sext)
v = SEXT(size, v);
else
v = ZEXT(size, v);
}
/* store value, unless it's R0 (on certain RISCs) */
if (regs == cpu->ptr_xr || !HAS_SPECIAL_GPR0(cpu) || index != 0)
new StoreInst(v, regs[index], bb);
return v;
}
/* disassemble an Alpha instruction */
void
md_print_insn(md_inst_t inst, /* instruction to disassemble */
md_addr_t pc, /* addr of inst, used for PC-rels */
FILE *stream) /* output stream */
{
enum md_opcode op;
/* use stderr as default output stream */
if (!stream)
stream = stderr;
/* decode the instruction, assumes predecoded text segment */
MD_SET_OPCODE(op, inst);
/* disassemble the instruction */
if (op <= OP_NA || op >= OP_MAX)
{
/* bogus instruction */
fprintf(stream, "<invalid inst: 0x%08x>", inst);
}
else
{
char *s;
fprintf(stream, "%-10s", MD_OP_NAME(op));
s = MD_OP_FORMAT(op);
while (*s) {
switch (*s) {
case 'a':
fprintf(stream, "r%d", RA);
break;
case 'b':
fprintf(stream, "r%d", RB);
break;
case 'c':
fprintf(stream, "r%d", RC);
break;
case 'A':
fprintf(stream, "f%d", RA);
break;
case 'B':
fprintf(stream, "f%d", RB);
break;
case 'C':
fprintf(stream, "f%d", RC);
break;
case 'o':
fprintf(stream, "%d", (sword_t)SEXT(OFS));
break;
case 'j':
myfprintf(stream, "0x%p", pc + (SEXT(OFS) << 2) + 4);
break;
case 'J':
myfprintf(stream, "0x%p", pc + (SEXT21(TARG) << 2) + 4);
break;
case 'i':
fprintf(stream, "%d", (word_t)IMM);
break;
default:
/* anything unrecognized, e.g., '.' is just passed through */
fputc(*s, stream);
}
s++;
}
}
}
