/*int wmt_sf_resume(struct device *dev)*/
int wmt_sf_resume(struct platform_device *pdev)
{
/*struct platform_device *pdev = to_platform_device(dev);*/
struct wmt_sf_info_t *info = dev_get_drvdata(&pdev->dev);
struct sfreg_t *sfreg = info->reg;
printk(KERN_INFO "gri pmc_wake_sts=0x%x\n",pmc_wake_sts);
REG32_VAL(PMCEU_ADDR) |= SF_CLOCK_EN;
if (info->reg)
config_sf_reg(info->reg);
else
printk(KERN_ERR "wmt sf restore state error\n");
if (g_sf_info[0].id == SF_IDALL(ATMEL_MANUF, AT_25DF041A_ID)) {
printk(KERN_INFO "sf resume and set Global Unprotect\n");
sfreg->SPI_INTF_CFG |= SF_MANUAL_MODE; /* enter programmable command mode */
sfreg->SPI_PROG_CMD_WBF[0] = SF_CMD_WREN;
sfreg->SPI_PROG_CMD_CTR = (0x01000000 | (0<<1)); /* set size and chip select */
sfreg->SPI_PROG_CMD_CTR |= SF_RUN_CMD; /* enable programmable command */
while ((sfreg->SPI_PROG_CMD_CTR & SF_RUN_CMD) != 0)
;
sfreg->SPI_PROG_CMD_WBF[0] = SF_CMD_WRSR;
sfreg->SPI_PROG_CMD_WBF[1] = 0x00; /* Global Unprotect */
sfreg->SPI_PROG_CMD_CTR = (0x02000000 | (0<<1)); /* set size and chip select */
sfreg->SPI_PROG_CMD_CTR |= SF_RUN_CMD; /* enable programmable command */
while ((sfreg->SPI_PROG_CMD_CTR & SF_RUN_CMD) != 0)
;
sfreg->SPI_PROG_CMD_CTR = 0; /* reset programmable command register*/
sfreg->SPI_INTF_CFG &= ~SF_MANUAL_MODE; /* leave programmable mode */
}
REG32_VAL(PMCEU_ADDR) &= ~(SF_CLOCK_EN);/*Turn off the clock*/
return 0;
}
/* GD -Giga Device- */
#define GD_25Q40_ID 0x4013 /* 512KB */
#define GD_25Q128_ID 0x4018 /* 16MB */
#define SF_IDALL(x, y) ((x<<16)|y)
struct wm_sf_dev_t {
ulong id;
ulong size;
ulong sector_size;
};
struct wm_sf_dev_t sf_ids[] = {
/* {Device ID, Total Size, Sector Size} */
/* EON */
{SF_IDALL(EON_MANUF, EON_25P16_ID), 0x200000, 0x10000},
{SF_IDALL(EON_MANUF, EON_25P64_ID), 0x800000, 0x10000},
{SF_IDALL(EON_MANUF, EON_25F40_ID), 0x80000, 0x10000},
{SF_IDALL(EON_MANUF, EON_25F16_ID), 0x200000, 0x10000},
{SF_IDALL(EON_MANUF, EON_25Q64_ID), 0x800000, 0x10000},
/* NUMONYX */
{SF_IDALL(NUMONYX_MANUF, NX_25P16_ID), 0x200000, 0x10000},
{SF_IDALL(NUMONYX_MANUF, NX_25P64_ID), 0x800000, 0x10000},
/* MXIC */
{SF_IDALL(MXIC_MANUF, MX_L512_ID), 0x10000, 0x10000},
{SF_IDALL(MXIC_MANUF, MX_L4006E_ID), 0x80000, 0x10000},
{SF_IDALL(MXIC_MANUF, MX_L1605D_ID), 0x200000, 0x10000},
{SF_IDALL(MXIC_MANUF, MX_L3205D_ID), 0x400000, 0x10000},
{SF_IDALL(MXIC_MANUF, MX_L6405D_ID), 0x800000, 0x10000},
{SF_IDALL(MXIC_MANUF, MX_L1635D_ID), 0x200000, 0x10000},
{SF_IDALL(MXIC_MANUF, MX_L3235D_ID), 0x400000, 0x10000},
#include "wmt_sf.h"
/*
* Chip ID list
*
* Name. ID code, pagesize, chipsize in MegaByte, eraseblock size,
* options
*
* Pagesize; 0, 256, 512
* 0 get this information from the extended chip ID
+ 256 256 Byte page size
* 512 512 Byte page size
*/
struct wm_sf_dev_t sf_ids[] = {
/* EON */
{SF_IDALL(EON_MANUFACT, EON_25P16_ID), (2*1024)},
{SF_IDALL(EON_MANUFACT, EON_25P64_ID), (8*1024)},
{SF_IDALL(EON_MANUFACT, EON_25F40_ID), 512},
{SF_IDALL(EON_MANUFACT, EON_25F16_ID), (2*1024)},
{SF_IDALL(EON_MANUFACT, EON_25Q64_ID), (8*1024)},
/* NUMONYX */
{SF_IDALL(NUMONYX_MANUFACT, NX_25P16_ID), (2*1024)},
{SF_IDALL(NUMONYX_MANUFACT, NX_25P64_ID), (8*1024)},
/* MXIC */
{SF_IDALL(MXIC_MANUFACT, MX_L512_ID), 64},
{SF_IDALL(MXIC_MANUFACT, MX_L1605D_ID), (2*1024)},
{SF_IDALL(MXIC_MANUFACT, MX_L3205D_ID), (4*1024)},
{SF_IDALL(MXIC_MANUFACT, MX_L6405D_ID), (8*1024)},
{SF_IDALL(MXIC_MANUFACT, MX_L1635D_ID), (2*1024)},
{SF_IDALL(MXIC_MANUFACT, MX_L3235D_ID), (4*1024)},
{SF_IDALL(MXIC_MANUFACT, MX_L12805D_ID), (16*1024)},
