/*!
*******************************************************************************
@Function SGXReset
@Description
Reset chip
@Input psDevInfo - device info. structure
@Input bHardwareRecovery - true if recovering powered hardware,
false if powering up
@Input ui32PDUMPFlags - flags to control PDUMP output
@Return IMG_VOID
******************************************************************************/
IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO *psDevInfo,
IMG_BOOL bHardwareRecovery,
IMG_UINT32 ui32PDUMPFlags)
#if !defined(SGX_FEATURE_MP)
{
IMG_UINT32 ui32RegVal;
#if defined(EUR_CR_BIF_INT_STAT_FAULT_REQ_MASK)
const IMG_UINT32 ui32BifFaultMask = EUR_CR_BIF_INT_STAT_FAULT_REQ_MASK;
#else
const IMG_UINT32 ui32BifFaultMask = EUR_CR_BIF_INT_STAT_FAULT_MASK;
#endif
#if !defined(PDUMP)
PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
#endif /* PDUMP */
PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Start of SGX reset sequence\r\n");
#if defined(FIX_HW_BRN_23944)
/* Pause the BIF. */
ui32RegVal = EUR_CR_BIF_CTRL_PAUSE_MASK;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
ui32RegVal = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_INT_STAT);
if (ui32RegVal & ui32BifFaultMask)
{
/* Page fault needs to be cleared before resetting the BIF. */
ui32RegVal = EUR_CR_BIF_CTRL_PAUSE_MASK | EUR_CR_BIF_CTRL_CLEAR_FAULT_MASK;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
ui32RegVal = EUR_CR_BIF_CTRL_PAUSE_MASK;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
}
#endif /* defined(FIX_HW_BRN_23944) */
/* Reset all including BIF */
SGXResetSoftReset(psDevInfo, IMG_TRUE, ui32PDUMPFlags, IMG_TRUE);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
/*
Initialise the BIF state.
*/
#if defined(SGX_FEATURE_36BIT_MMU)
/* enable 36bit addressing mode if the MMU supports it*/
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_36BIT_ADDRESSING, EUR_CR_BIF_36BIT_ADDRESSING_ENABLE_MASK);
PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_36BIT_ADDRESSING, EUR_CR_BIF_36BIT_ADDRESSING_ENABLE_MASK, ui32PDUMPFlags);
#endif
SGXResetInitBIFContexts(psDevInfo, ui32PDUMPFlags);
#if defined(EUR_CR_BIF_MEM_ARB_CONFIG)
/*
Initialise the memory arbiter to its default state
*/
ui32RegVal = (12UL << EUR_CR_BIF_MEM_ARB_CONFIG_PAGE_SIZE_SHIFT) |
(7UL << EUR_CR_BIF_MEM_ARB_CONFIG_BEST_CNT_SHIFT) |
(12UL << EUR_CR_BIF_MEM_ARB_CONFIG_TTE_THRESH_SHIFT);
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_MEM_ARB_CONFIG, ui32RegVal);
PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_MEM_ARB_CONFIG, ui32RegVal, ui32PDUMPFlags);
#endif /* EUR_CR_BIF_MEM_ARB_CONFIG */
#if defined(SGX_FEATURE_SYSTEM_CACHE)
#if defined(SGX_BYPASS_SYSTEM_CACHE)
/* set the SLC to bypass all accesses */
ui32RegVal = MNE_CR_CTRL_BYPASS_ALL_MASK;
#else
#if defined(FIX_HW_BRN_26620)
ui32RegVal = 0;
#else
/* set the SLC to bypass cache-coherent accesses */
ui32RegVal = MNE_CR_CTRL_BYP_CC_MASK;
#endif
#if defined(FIX_HW_BRN_34028)
/* Bypass the MNE for the USEC requester */
ui32RegVal |= (8 << MNE_CR_CTRL_BYPASS_SHIFT);
#endif
#endif /* SGX_BYPASS_SYSTEM_CACHE */
OSWriteHWReg(psDevInfo->pvRegsBaseKM, MNE_CR_CTRL, ui32RegVal);
PDUMPREG(SGX_PDUMPREG_NAME, MNE_CR_CTRL, ui32RegVal);
#endif /* SGX_FEATURE_SYSTEM_CACHE */
if (bHardwareRecovery)
{
/*
Set all requestors to the dummy PD which forces all memory
accesses to page fault.
This enables us to flush out BIF requests from parts of SGX
which do not have their own soft reset.
Note: sBIFResetPDDevPAddr.uiAddr is a relative address (2GB max)
MSB is the bus master flag; 1 == enabled
*/
ui32RegVal = (IMG_UINT32)psDevInfo->sBIFResetPDDevPAddr.uiAddr;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
/* Bring BIF out of reset. */
SGXResetSoftReset(psDevInfo, IMG_FALSE, ui32PDUMPFlags, IMG_TRUE);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
SGXResetInvalDC(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
/*
Check for a page fault from parts of SGX which do not have a reset.
*/
for (;;)
{
IMG_UINT32 ui32BifIntStat = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_INT_STAT);
IMG_DEV_VIRTADDR sBifFault;
IMG_UINT32 ui32PDIndex, ui32PTIndex;
if ((ui32BifIntStat & ui32BifFaultMask) == 0)
{
break;
}
/*
There is a page fault, so reset the BIF again, map in the dummy page,
bring the BIF up and invalidate the Directory Cache.
*/
sBifFault.uiAddr = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_FAULT);
PVR_DPF((PVR_DBG_WARNING, "SGXReset: Page fault 0x%x/0x%x", ui32BifIntStat, sBifFault.uiAddr));
ui32PDIndex = sBifFault.uiAddr >> (SGX_MMU_PAGE_SHIFT + SGX_MMU_PT_SHIFT);
ui32PTIndex = (sBifFault.uiAddr & SGX_MMU_PT_MASK) >> SGX_MMU_PAGE_SHIFT;
/* Put the BIF into reset. */
SGXResetSoftReset(psDevInfo, IMG_TRUE, ui32PDUMPFlags, IMG_FALSE);
/* Map in the dummy page. */
psDevInfo->pui32BIFResetPD[ui32PDIndex] = (psDevInfo->sBIFResetPTDevPAddr.uiAddr
>>SGX_MMU_PDE_ADDR_ALIGNSHIFT)
| SGX_MMU_PDE_PAGE_SIZE_4K
| SGX_MMU_PDE_VALID;
psDevInfo->pui32BIFResetPT[ui32PTIndex] = (psDevInfo->sBIFResetPageDevPAddr.uiAddr
>>SGX_MMU_PTE_ADDR_ALIGNSHIFT)
| SGX_MMU_PTE_VALID;
/* Clear outstanding events. */
ui32RegVal = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS);
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR, ui32RegVal);
ui32RegVal = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS2);
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR2, ui32RegVal);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
/* Bring the BIF out of reset. */
SGXResetSoftReset(psDevInfo, IMG_FALSE, ui32PDUMPFlags, IMG_FALSE);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
/* Invalidate Directory Cache. */
SGXResetInvalDC(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
/* Unmap the dummy page and try again. */
psDevInfo->pui32BIFResetPD[ui32PDIndex] = 0;
psDevInfo->pui32BIFResetPT[ui32PTIndex] = 0;
}
}
else
{
IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO *psDevInfo,
IMG_BOOL bHardwareRecovery,
IMG_UINT32 ui32PDUMPFlags)
#if !defined(SGX_FEATURE_MP)
{
IMG_UINT32 ui32RegVal;
#if defined(EUR_CR_BIF_INT_STAT_FAULT_REQ_MASK)
const IMG_UINT32 ui32BifFaultMask = EUR_CR_BIF_INT_STAT_FAULT_REQ_MASK;
#else
const IMG_UINT32 ui32BifFaultMask = EUR_CR_BIF_INT_STAT_FAULT_MASK;
#endif
#if !defined(PDUMP)
PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
#endif
PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Start of SGX reset sequence\r\n");
#if defined(FIX_HW_BRN_23944)
ui32RegVal = EUR_CR_BIF_CTRL_PAUSE_MASK;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
ui32RegVal = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_INT_STAT);
if (ui32RegVal & ui32BifFaultMask)
{
ui32RegVal = EUR_CR_BIF_CTRL_PAUSE_MASK | EUR_CR_BIF_CTRL_CLEAR_FAULT_MASK;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
ui32RegVal = EUR_CR_BIF_CTRL_PAUSE_MASK;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
}
#endif
SGXResetSoftReset(psDevInfo, IMG_TRUE, ui32PDUMPFlags, IMG_TRUE);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
#if defined(SGX_FEATURE_36BIT_MMU)
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_36BIT_ADDRESSING, EUR_CR_BIF_36BIT_ADDRESSING_ENABLE_MASK);
PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_36BIT_ADDRESSING, EUR_CR_BIF_36BIT_ADDRESSING_ENABLE_MASK, ui32PDUMPFlags);
#endif
SGXResetInitBIFContexts(psDevInfo, ui32PDUMPFlags);
#if defined(EUR_CR_BIF_MEM_ARB_CONFIG)
ui32RegVal = (12UL << EUR_CR_BIF_MEM_ARB_CONFIG_PAGE_SIZE_SHIFT) |
(7UL << EUR_CR_BIF_MEM_ARB_CONFIG_BEST_CNT_SHIFT) |
(12UL << EUR_CR_BIF_MEM_ARB_CONFIG_TTE_THRESH_SHIFT);
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_MEM_ARB_CONFIG, ui32RegVal);
PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_MEM_ARB_CONFIG, ui32RegVal, ui32PDUMPFlags);
#endif
#if defined(SGX_FEATURE_SYSTEM_CACHE)
#if defined(SGX_BYPASS_SYSTEM_CACHE)
ui32RegVal = MNE_CR_CTRL_BYPASS_ALL_MASK;
#else
#if defined(FIX_HW_BRN_26620)
ui32RegVal = 0;
#else
ui32RegVal = MNE_CR_CTRL_BYP_CC_MASK;
#endif
#if defined(FIX_HW_BRN_34028)
ui32RegVal |= (8 << MNE_CR_CTRL_BYPASS_SHIFT);
#endif
#endif
OSWriteHWReg(psDevInfo->pvRegsBaseKM, MNE_CR_CTRL, ui32RegVal);
PDUMPREG(SGX_PDUMPREG_NAME, MNE_CR_CTRL, ui32RegVal);
#endif
if (bHardwareRecovery)
{
ui32RegVal = (IMG_UINT32)psDevInfo->sBIFResetPDDevPAddr.uiAddr;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
SGXResetSoftReset(psDevInfo, IMG_FALSE, ui32PDUMPFlags, IMG_TRUE);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
SGXResetInvalDC(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
for (;;)
{
IMG_UINT32 ui32BifIntStat = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_INT_STAT);
IMG_DEV_VIRTADDR sBifFault;
IMG_UINT32 ui32PDIndex, ui32PTIndex;
if ((ui32BifIntStat & ui32BifFaultMask) == 0)
{
break;
}
sBifFault.uiAddr = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_FAULT);
PVR_DPF((PVR_DBG_WARNING, "SGXReset: Page fault 0x%x/0x%x", ui32BifIntStat, sBifFault.uiAddr));
ui32PDIndex = sBifFault.uiAddr >> (SGX_MMU_PAGE_SHIFT + SGX_MMU_PT_SHIFT);
ui32PTIndex = (sBifFault.uiAddr & SGX_MMU_PT_MASK) >> SGX_MMU_PAGE_SHIFT;
SGXResetSoftReset(psDevInfo, IMG_TRUE, ui32PDUMPFlags, IMG_FALSE);
psDevInfo->pui32BIFResetPD[ui32PDIndex] = (psDevInfo->sBIFResetPTDevPAddr.uiAddr
>>SGX_MMU_PDE_ADDR_ALIGNSHIFT)
| SGX_MMU_PDE_PAGE_SIZE_4K
| SGX_MMU_PDE_VALID;
psDevInfo->pui32BIFResetPT[ui32PTIndex] = (psDevInfo->sBIFResetPageDevPAddr.uiAddr
>>SGX_MMU_PTE_ADDR_ALIGNSHIFT)
| SGX_MMU_PTE_VALID;
ui32RegVal = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS);
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR, ui32RegVal);
ui32RegVal = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS2);
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR2, ui32RegVal);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
SGXResetSoftReset(psDevInfo, IMG_FALSE, ui32PDUMPFlags, IMG_FALSE);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
SGXResetInvalDC(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
psDevInfo->pui32BIFResetPD[ui32PDIndex] = 0;
psDevInfo->pui32BIFResetPT[ui32PTIndex] = 0;
}
}
else
{
IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO *psDevInfo,
IMG_UINT32 ui32PDUMPFlags)
{
IMG_UINT32 ui32RegVal;
#if defined(EUR_CR_BIF_INT_STAT_FAULT_REQ_MASK)
const IMG_UINT32 ui32BifFaultMask = EUR_CR_BIF_INT_STAT_FAULT_REQ_MASK;
#else
const IMG_UINT32 ui32BifFaultMask = EUR_CR_BIF_INT_STAT_FAULT_MASK;
#endif
#ifndef PDUMP
PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
#endif
psDevInfo->ui32NumResets++;
PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Start of SGX reset sequence\r\n");
#if defined(FIX_HW_BRN_23944)
ui32RegVal = EUR_CR_BIF_CTRL_PAUSE_MASK;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
PDUMPREGWITHFLAGS(EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
ui32RegVal = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_INT_STAT);
if (ui32RegVal & ui32BifFaultMask)
{
ui32RegVal = EUR_CR_BIF_CTRL_PAUSE_MASK | EUR_CR_BIF_CTRL_CLEAR_FAULT_MASK;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
PDUMPREGWITHFLAGS(EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
ui32RegVal = EUR_CR_BIF_CTRL_PAUSE_MASK;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
PDUMPREGWITHFLAGS(EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
}
#endif
SGXResetSoftReset(psDevInfo, IMG_TRUE, ui32PDUMPFlags, IMG_TRUE);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
#if defined(SGX_FEATURE_36BIT_MMU)
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_36BIT_ADDRESSING, EUR_CR_BIF_36BIT_ADDRESSING_ENABLE_MASK);
PDUMPREGWITHFLAGS(EUR_CR_BIF_36BIT_ADDRESSING, EUR_CR_BIF_36BIT_ADDRESSING_ENABLE_MASK, ui32PDUMPFlags);
#endif
ui32RegVal = 0;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
PDUMPREGWITHFLAGS(EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
#if defined(SGX_FEATURE_MP)
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_BIF_CTRL, ui32RegVal);
PDUMPREGWITHFLAGS(EUR_CR_MASTER_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
#endif
#if defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_BANK_SET, ui32RegVal);
PDUMPREGWITHFLAGS(EUR_CR_BIF_BANK_SET, ui32RegVal, ui32PDUMPFlags);
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_BANK0, ui32RegVal);
PDUMPREGWITHFLAGS(EUR_CR_BIF_BANK0, ui32RegVal, ui32PDUMPFlags);
#endif
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal);
PDUMPREGWITHFLAGS(EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal, ui32PDUMPFlags);
#if defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
{
IMG_UINT32 ui32DirList, ui32DirListReg;
for (ui32DirList = 1;
ui32DirList < SGX_FEATURE_BIF_NUM_DIRLISTS;
ui32DirList++)
{
ui32DirListReg = EUR_CR_BIF_DIR_LIST_BASE1 + 4 * (ui32DirList - 1);
OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32DirListReg, ui32RegVal);
PDUMPREGWITHFLAGS(ui32DirListReg, ui32RegVal, ui32PDUMPFlags);
}
}
#endif
#if defined(EUR_CR_BIF_MEM_ARB_CONFIG)
ui32RegVal = (12UL << EUR_CR_BIF_MEM_ARB_CONFIG_PAGE_SIZE_SHIFT) |
(7UL << EUR_CR_BIF_MEM_ARB_CONFIG_BEST_CNT_SHIFT) |
(12UL << EUR_CR_BIF_MEM_ARB_CONFIG_TTE_THRESH_SHIFT);
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_MEM_ARB_CONFIG, ui32RegVal);
PDUMPREGWITHFLAGS(EUR_CR_BIF_MEM_ARB_CONFIG, ui32RegVal, ui32PDUMPFlags);
#endif
#if defined(SGX_FEATURE_SYSTEM_CACHE)
#if defined(SGX_FEATURE_MP)
#if defined(SGX_BYPASS_SYSTEM_CACHE)
#error SGX_BYPASS_SYSTEM_CACHE not supported
#else
ui32RegVal = EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ0_MASK |
(0xC << EUR_CR_MASTER_SLC_CTRL_ARB_PAGE_SIZE_SHIFT);
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SLC_CTRL, ui32RegVal);
PDUMPREG(EUR_CR_MASTER_SLC_CTRL, ui32RegVal);
ui32RegVal = EUR_CR_MASTER_SLC_CTRL_BYPASS_BYP_CC_MASK;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SLC_CTRL_BYPASS, ui32RegVal);
PDUMPREG(EUR_CR_MASTER_SLC_CTRL_BYPASS, ui32RegVal);
#endif
#else
#if defined(SGX_BYPASS_SYSTEM_CACHE)
ui32RegVal = EUR_CR_MNE_CR_CTRL_BYPASS_ALL_MASK;
#else
#if defined(FIX_HW_BRN_26620)
ui32RegVal = 0;
#else
ui32RegVal = EUR_CR_MNE_CR_CTRL_BYP_CC_MASK;
#endif
#endif
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MNE_CR_CTRL, ui32RegVal);
PDUMPREG(EUR_CR_MNE_CR_CTRL, ui32RegVal);
#endif
#endif
ui32RegVal = psDevInfo->sBIFResetPDDevPAddr.uiAddr;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
SGXResetSoftReset(psDevInfo, IMG_FALSE, ui32PDUMPFlags, IMG_TRUE);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
SGXResetInvalDC(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
for (;;)
{
IMG_UINT32 ui32BifIntStat = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_INT_STAT);
IMG_DEV_VIRTADDR sBifFault;
IMG_UINT32 ui32PDIndex, ui32PTIndex;
if ((ui32BifIntStat & ui32BifFaultMask) == 0)
{
break;
}
sBifFault.uiAddr = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_FAULT);
PVR_DPF((PVR_DBG_WARNING, "SGXReset: Page fault 0x%x/0x%x", ui32BifIntStat, sBifFault.uiAddr));
ui32PDIndex = sBifFault.uiAddr >> (SGX_MMU_PAGE_SHIFT + SGX_MMU_PT_SHIFT);
ui32PTIndex = (sBifFault.uiAddr & SGX_MMU_PT_MASK) >> SGX_MMU_PAGE_SHIFT;
SGXResetSoftReset(psDevInfo, IMG_TRUE, ui32PDUMPFlags, IMG_FALSE);
psDevInfo->pui32BIFResetPD[ui32PDIndex] = (psDevInfo->sBIFResetPTDevPAddr.uiAddr
>>SGX_MMU_PDE_ADDR_ALIGNSHIFT)
| SGX_MMU_PDE_PAGE_SIZE_4K
| SGX_MMU_PDE_VALID;
psDevInfo->pui32BIFResetPT[ui32PTIndex] = (psDevInfo->sBIFResetPageDevPAddr.uiAddr
>>SGX_MMU_PTE_ADDR_ALIGNSHIFT)
| SGX_MMU_PTE_VALID;
ui32RegVal = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS);
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR, ui32RegVal);
ui32RegVal = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS2);
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR2, ui32RegVal);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
SGXResetSoftReset(psDevInfo, IMG_FALSE, ui32PDUMPFlags, IMG_FALSE);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
SGXResetInvalDC(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
psDevInfo->pui32BIFResetPD[ui32PDIndex] = 0;
psDevInfo->pui32BIFResetPT[ui32PTIndex] = 0;
}
#if defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
ui32RegVal = (SGX_BIF_DIR_LIST_INDEX_EDM << EUR_CR_BIF_BANK0_INDEX_EDM_SHIFT);
#if defined(SGX_FEATURE_2D_HARDWARE)
ui32RegVal |= (SGX_BIF_DIR_LIST_INDEX_EDM << EUR_CR_BIF_BANK0_INDEX_2D_SHIFT);
#endif
#if defined(FIX_HW_BRN_23410)
ui32RegVal |= (SGX_BIF_DIR_LIST_INDEX_EDM << EUR_CR_BIF_BANK0_INDEX_TA_SHIFT);
#endif
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_BANK0, ui32RegVal);
PDUMPREGWITHFLAGS(EUR_CR_BIF_BANK0, ui32RegVal, ui32PDUMPFlags);
#endif
{
IMG_UINT32 ui32EDMDirListReg;
#if (SGX_BIF_DIR_LIST_INDEX_EDM == 0)
ui32EDMDirListReg = EUR_CR_BIF_DIR_LIST_BASE0;
#else
ui32EDMDirListReg = EUR_CR_BIF_DIR_LIST_BASE1 + 4 * (SGX_BIF_DIR_LIST_INDEX_EDM - 1);
#endif
#if defined(FIX_HW_BRN_28011)
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_DIR_LIST_BASE0, psDevInfo->sKernelPDDevPAddr.uiAddr>>SGX_MMU_PDE_ADDR_ALIGNSHIFT);
PDUMPPDREGWITHFLAGS(EUR_CR_BIF_DIR_LIST_BASE0, psDevInfo->sKernelPDDevPAddr.uiAddr>>SGX_MMU_PDE_ADDR_ALIGNSHIFT, ui32PDUMPFlags, PDUMP_PD_UNIQUETAG);
#endif
OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32EDMDirListReg, psDevInfo->sKernelPDDevPAddr.uiAddr>>SGX_MMU_PDE_ADDR_ALIGNSHIFT);
PDUMPPDREGWITHFLAGS(ui32EDMDirListReg, psDevInfo->sKernelPDDevPAddr.uiAddr>>SGX_MMU_PDE_ADDR_ALIGNSHIFT, ui32PDUMPFlags, PDUMP_PD_UNIQUETAG);
}
#ifdef SGX_FEATURE_2D_HARDWARE
#if ((SGX_2D_HEAP_BASE & ~EUR_CR_BIF_TWOD_REQ_BASE_ADDR_MASK) != 0)
#error "SGXReset: SGX_2D_HEAP_BASE doesn't match EUR_CR_BIF_TWOD_REQ_BASE_ADDR_MASK alignment"
#endif
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_TWOD_REQ_BASE, SGX_2D_HEAP_BASE);
PDUMPREGWITHFLAGS(EUR_CR_BIF_TWOD_REQ_BASE, SGX_2D_HEAP_BASE, ui32PDUMPFlags);
#endif
SGXResetInvalDC(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
PVR_DPF((PVR_DBG_MESSAGE,"Soft Reset of SGX"));
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
ui32RegVal = 0;
#if defined(SGX_FEATURE_MP)
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SOFT_RESET, ui32RegVal);
PDUMPREGWITHFLAGS(EUR_CR_MASTER_SOFT_RESET, ui32RegVal, ui32PDUMPFlags);
#endif
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_SOFT_RESET, ui32RegVal);
PDUMPREGWITHFLAGS(EUR_CR_SOFT_RESET, ui32RegVal, ui32PDUMPFlags);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "End of SGX reset sequence\r\n");
}
void SGXReset(struct PVRSRV_SGXDEV_INFO *psDevInfo, u32 ui32PDUMPFlags)
{
u32 ui32RegVal;
const u32 ui32BifFaultMask = EUR_CR_BIF_INT_STAT_FAULT_MASK;
#ifndef PDUMP
PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
#endif
psDevInfo->ui32NumResets++;
PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags,
"Start of SGX reset sequence\r\n");
#if defined(FIX_HW_BRN_23944)
ui32RegVal = EUR_CR_BIF_CTRL_PAUSE_MASK;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
PDUMPREGWITHFLAGS(EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
ui32RegVal = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_INT_STAT);
if (ui32RegVal & ui32BifFaultMask) {
ui32RegVal =
EUR_CR_BIF_CTRL_PAUSE_MASK |
EUR_CR_BIF_CTRL_CLEAR_FAULT_MASK;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL,
ui32RegVal);
PDUMPREGWITHFLAGS(EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
ui32RegVal = EUR_CR_BIF_CTRL_PAUSE_MASK;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL,
ui32RegVal);
PDUMPREGWITHFLAGS(EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
}
#endif
SGXResetSoftReset(psDevInfo, IMG_TRUE, ui32PDUMPFlags, IMG_TRUE);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
ui32RegVal = psDevInfo->sBIFResetPDDevPAddr.uiAddr;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_DIR_LIST_BASE0,
ui32RegVal);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
SGXResetSoftReset(psDevInfo, IMG_FALSE, ui32PDUMPFlags, IMG_TRUE);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
SGXResetInvalDC(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
for (;;) {
u32 ui32BifIntStat =
OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_INT_STAT);
struct IMG_DEV_VIRTADDR sBifFault;
u32 ui32PDIndex, ui32PTIndex;
if ((ui32BifIntStat & ui32BifFaultMask) == 0)
break;
sBifFault.uiAddr =
OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_FAULT);
PVR_DPF(PVR_DBG_WARNING, "SGXReset: Page fault 0x%x/0x%x",
ui32BifIntStat, sBifFault.uiAddr);
ui32PDIndex =
sBifFault.uiAddr >> (SGX_MMU_PAGE_SHIFT + SGX_MMU_PT_SHIFT);
ui32PTIndex =
(sBifFault.uiAddr & SGX_MMU_PT_MASK) >> SGX_MMU_PAGE_SHIFT;
SGXResetSoftReset(psDevInfo, IMG_TRUE, ui32PDUMPFlags,
IMG_FALSE);
psDevInfo->pui32BIFResetPD[ui32PDIndex] =
psDevInfo->sBIFResetPTDevPAddr.uiAddr | SGX_MMU_PDE_VALID;
psDevInfo->pui32BIFResetPT[ui32PTIndex] =
psDevInfo->sBIFResetPageDevPAddr.uiAddr | SGX_MMU_PTE_VALID;
ui32RegVal =
OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS);
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR,
ui32RegVal);
ui32RegVal =
OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS2);
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR2,
ui32RegVal);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
SGXResetSoftReset(psDevInfo, IMG_FALSE, ui32PDUMPFlags,
IMG_FALSE);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
SGXResetInvalDC(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
psDevInfo->pui32BIFResetPD[ui32PDIndex] = 0;
psDevInfo->pui32BIFResetPT[ui32PTIndex] = 0;
}
OSWriteHWReg(psDevInfo->pvRegsBaseKM, SGX_BIF_DIR_LIST_REG_EDM,
psDevInfo->sKernelPDDevPAddr.uiAddr);
PDUMPPDREGWITHFLAGS(SGX_BIF_DIR_LIST_REG_EDM,
psDevInfo->sKernelPDDevPAddr.uiAddr, ui32PDUMPFlags,
PDUMP_PD_UNIQUETAG);
SGXResetInvalDC(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
PVR_DPF(PVR_DBG_WARNING, "Soft Reset of SGX");
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
ui32RegVal = 0;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_SOFT_RESET, ui32RegVal);
PDUMPREGWITHFLAGS(EUR_CR_SOFT_RESET, ui32RegVal, ui32PDUMPFlags);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "End of SGX reset sequence\r\n");
}
IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO *psDevInfo,
IMG_BOOL bHardwareRecovery,
IMG_UINT32 ui32PDUMPFlags)
{
IMG_UINT32 ui32RegVal;
#if defined(EUR_CR_BIF_INT_STAT_FAULT_REQ_MASK)
const IMG_UINT32 ui32BifFaultMask = EUR_CR_BIF_INT_STAT_FAULT_REQ_MASK;
#else
const IMG_UINT32 ui32BifFaultMask = EUR_CR_BIF_INT_STAT_FAULT_MASK;
#endif
#ifndef PDUMP
PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
#endif
psDevInfo->ui32NumResets++;
PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Start of SGX reset sequence\r\n");
#if defined(FIX_HW_BRN_23944)
ui32RegVal = EUR_CR_BIF_CTRL_PAUSE_MASK;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
ui32RegVal = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_INT_STAT);
if (ui32RegVal & ui32BifFaultMask)
{
ui32RegVal = EUR_CR_BIF_CTRL_PAUSE_MASK | EUR_CR_BIF_CTRL_CLEAR_FAULT_MASK;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
ui32RegVal = EUR_CR_BIF_CTRL_PAUSE_MASK;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
}
#endif
SGXResetSoftReset(psDevInfo, IMG_TRUE, ui32PDUMPFlags, IMG_TRUE);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
#if defined(SGX_FEATURE_36BIT_MMU)
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_36BIT_ADDRESSING, EUR_CR_BIF_36BIT_ADDRESSING_ENABLE_MASK);
PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_36BIT_ADDRESSING, EUR_CR_BIF_36BIT_ADDRESSING_ENABLE_MASK, ui32PDUMPFlags);
#endif
ui32RegVal = 0;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
#if defined(SGX_FEATURE_MP)
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_BIF_CTRL, ui32RegVal);
PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_MASTER_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
#endif
#if defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_BANK_SET, ui32RegVal);
PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_BANK_SET, ui32RegVal, ui32PDUMPFlags);
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_BANK0, ui32RegVal);
PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_BANK0, ui32RegVal, ui32PDUMPFlags);
#endif
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal);
PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal, ui32PDUMPFlags);
#if defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
{
IMG_UINT32 ui32DirList, ui32DirListReg;
for (ui32DirList = 1;
ui32DirList < SGX_FEATURE_BIF_NUM_DIRLISTS;
ui32DirList++)
{
ui32DirListReg = EUR_CR_BIF_DIR_LIST_BASE1 + 4 * (ui32DirList - 1);
OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32DirListReg, ui32RegVal);
PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, ui32DirListReg, ui32RegVal, ui32PDUMPFlags);
}
}
#endif
#if defined(EUR_CR_BIF_MEM_ARB_CONFIG)
ui32RegVal = (12UL << EUR_CR_BIF_MEM_ARB_CONFIG_PAGE_SIZE_SHIFT) |
(7UL << EUR_CR_BIF_MEM_ARB_CONFIG_BEST_CNT_SHIFT) |
(12UL << EUR_CR_BIF_MEM_ARB_CONFIG_TTE_THRESH_SHIFT);
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_MEM_ARB_CONFIG, ui32RegVal);
PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_MEM_ARB_CONFIG, ui32RegVal, ui32PDUMPFlags);
#endif
#if defined(SGX_FEATURE_SYSTEM_CACHE)
#if defined(SGX_FEATURE_MP)
#if defined(SGX_BYPASS_SYSTEM_CACHE)
#error SGX_BYPASS_SYSTEM_CACHE not supported
#else
ui32RegVal = EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ0_MASK |
#if defined(FIX_HW_BRN_30954)
EUR_CR_MASTER_SLC_CTRL_DISABLE_REORDERING_MASK |
#endif
(0xC << EUR_CR_MASTER_SLC_CTRL_ARB_PAGE_SIZE_SHIFT);
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SLC_CTRL, ui32RegVal);
PDUMPREG(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SLC_CTRL, ui32RegVal);
ui32RegVal = EUR_CR_MASTER_SLC_CTRL_BYPASS_BYP_CC_MASK;
#if defined(FIX_HW_BRN_31195)
ui32RegVal |= EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE0_MASK |
EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE1_MASK |
EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE2_MASK |
EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE3_MASK |
EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_TA_MASK;
#endif
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SLC_CTRL_BYPASS, ui32RegVal);
PDUMPREG(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SLC_CTRL_BYPASS, ui32RegVal);
#endif
#else
#if defined(SGX_BYPASS_SYSTEM_CACHE)
ui32RegVal = MNE_CR_CTRL_BYPASS_ALL_MASK;
#else
#if defined(FIX_HW_BRN_26620)
ui32RegVal = 0;
#else
ui32RegVal = MNE_CR_CTRL_BYP_CC_MASK;
#endif
#endif
OSWriteHWReg(psDevInfo->pvRegsBaseKM, MNE_CR_CTRL, ui32RegVal);
PDUMPREG(SGX_PDUMPREG_NAME, MNE_CR_CTRL, ui32RegVal);
#endif
#endif
if (bHardwareRecovery)
{
ui32RegVal = (IMG_UINT32)psDevInfo->sBIFResetPDDevPAddr.uiAddr;
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
SGXResetSoftReset(psDevInfo, IMG_FALSE, ui32PDUMPFlags, IMG_TRUE);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
SGXResetInvalDC(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
for (;;)
{
IMG_UINT32 ui32BifIntStat = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_INT_STAT);
IMG_DEV_VIRTADDR sBifFault;
IMG_UINT32 ui32PDIndex, ui32PTIndex;
if ((ui32BifIntStat & ui32BifFaultMask) == 0)
{
break;
}
sBifFault.uiAddr = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_FAULT);
PVR_DPF((PVR_DBG_WARNING, "SGXReset: Page fault 0x%x/0x%x", ui32BifIntStat, sBifFault.uiAddr));
ui32PDIndex = sBifFault.uiAddr >> (SGX_MMU_PAGE_SHIFT + SGX_MMU_PT_SHIFT);
ui32PTIndex = (sBifFault.uiAddr & SGX_MMU_PT_MASK) >> SGX_MMU_PAGE_SHIFT;
SGXResetSoftReset(psDevInfo, IMG_TRUE, ui32PDUMPFlags, IMG_FALSE);
psDevInfo->pui32BIFResetPD[ui32PDIndex] = (psDevInfo->sBIFResetPTDevPAddr.uiAddr
>>SGX_MMU_PDE_ADDR_ALIGNSHIFT)
| SGX_MMU_PDE_PAGE_SIZE_4K
| SGX_MMU_PDE_VALID;
psDevInfo->pui32BIFResetPT[ui32PTIndex] = (psDevInfo->sBIFResetPageDevPAddr.uiAddr
>>SGX_MMU_PTE_ADDR_ALIGNSHIFT)
| SGX_MMU_PTE_VALID;
ui32RegVal = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS);
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR, ui32RegVal);
ui32RegVal = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS2);
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR2, ui32RegVal);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
SGXResetSoftReset(psDevInfo, IMG_FALSE, ui32PDUMPFlags, IMG_FALSE);
SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
SGXResetInvalDC(psDevInfo, ui32PDUMPFlags, IMG_FALSE);
psDevInfo->pui32BIFResetPD[ui32PDIndex] = 0;
psDevInfo->pui32BIFResetPT[ui32PTIndex] = 0;
}
}
else
{
