/* Initialization routine for the NFC. This function will enable
* NFC pin functions for all of the required pins and perform
* basic initialization of the NFC based on the port size and
* chip select specified by the nand.h file.
*
* Parameters:
* none
*/
void nand_init(void)
{
/* Enable the NFC clock gate in the SIM */
SIM_SCGC3 |= SIM_SCGC3_NFC_MASK;
/* Disable the MPU to allow NFC to access memory */
MPU_CESR &= 0xFFFFFFFE;
/* Set the NFC clock divder according to defines in nand.h */
SIM_CLKDIV4 |= SIM_CLKDIV4_NFCDIV(NFCDIV) |SIM_CLKDIV4_NFCFRAC(NFCFRAC);
/* Make sure that NFC_CE is defined */
#if (!(defined(NFC_CE)))
#error "NFC_CE must be defined in nand.h"
#endif
/* Enable the chip select in the NFC and enable the pad for the CS */
if(NFC_CE == NFC_CE0)
{
NFC_RAR |= (NFC_RAR_CS0_MASK | NFC_RAR_RB0_MASK);
PORTC_PCR17 = PORT_PCR_MUX(6) | PORT_PCR_DSE_MASK; /* Enable NFC_CE0 pad */
}
else /* (NFC_CE == NFC_CE1) */
{
NFC_RAR |= (NFC_RAR_CS1_MASK | NFC_RAR_RB1_MASK);
PORTC_PCR18 = PORT_PCR_MUX(6) | PORT_PCR_DSE_MASK; /* Enable NFC_CE0 pad */
}
/* Enable all of the NFC control signal pads */
PORTC_PCR16 = PORT_PCR_MUX(6) | PORT_PCR_DSE_MASK; /* Enable the NFC_RB pad */
PORTD_PCR8 = PORT_PCR_MUX(6) | PORT_PCR_DSE_MASK; /* Enable the NFC_CLE pad */
PORTD_PCR9 = PORT_PCR_MUX(6) | PORT_PCR_DSE_MASK; /* Enable the NFC_ALE pad */
PORTD_PCR10 = PORT_PCR_MUX(6) | PORT_PCR_DSE_MASK; /* Enable the NFC_RE pad */
PORTC_PCR11 = PORT_PCR_MUX(5) | PORT_PCR_DSE_MASK; /* Enable the NFC_WE pad */
/* Configure bit width in NFC and enable the NFC_IO pins based on the
* defined port size in nand.h.
*/
if (DATA_WIDTH == NFC_16BIT)
{
NFC_CFG |= NFC_CFG_BITWIDTH_MASK;
PORTB_PCR20 = PORT_PCR_MUX(5) | PORT_PCR_DSE_MASK; /* Enable the NFC_DATA15 pad */
PORTB_PCR21 = PORT_PCR_MUX(5) | PORT_PCR_DSE_MASK; /* Enable the NFC_DATA14 pad */
PORTB_PCR22 = PORT_PCR_MUX(5) | PORT_PCR_DSE_MASK; /* Enable the NFC_DATA13 pad */
PORTB_PCR23 = PORT_PCR_MUX(5) | PORT_PCR_DSE_MASK; /* Enable the NFC_DATA12 pad */
PORTC_PCR0 = PORT_PCR_MUX(5) | PORT_PCR_DSE_MASK; /* Enable the NFC_DATA11 pad */
PORTC_PCR1 = PORT_PCR_MUX(5) | PORT_PCR_DSE_MASK; /* Enable the NFC_DATA10 pad */
PORTC_PCR2 = PORT_PCR_MUX(5) | PORT_PCR_DSE_MASK; /* Enable the NFC_DATA9 pad */
PORTC_PCR4 = PORT_PCR_MUX(5) | PORT_PCR_DSE_MASK; /* Enable the NFC_DATA8 pad */
PORTC_PCR5 = PORT_PCR_MUX(5) | PORT_PCR_DSE_MASK; /* Enable the NFC_DATA7 pad */
PORTC_PCR6 = PORT_PCR_MUX(5) | PORT_PCR_DSE_MASK; /* Enable the NFC_DATA6 pad */
PORTC_PCR7 = PORT_PCR_MUX(5) | PORT_PCR_DSE_MASK; /* Enable the NFC_DATA5 pad */
PORTC_PCR8 = PORT_PCR_MUX(5) | PORT_PCR_DSE_MASK; /* Enable the NFC_DATA4 pad */
PORTC_PCR9 = PORT_PCR_MUX(5) | PORT_PCR_DSE_MASK; /* Enable the NFC_DATA3 pad */
PORTC_PCR10 = PORT_PCR_MUX(5) | PORT_PCR_DSE_MASK; /* Enable the NFC_DATA2 pad */
PORTD_PCR4 = PORT_PCR_MUX(5) | PORT_PCR_DSE_MASK; /* Enable the NFC_DATA1 pad */
PORTD_PCR5 = PORT_PCR_MUX(5) | PORT_PCR_DSE_MASK; /* Enable the NFC_DATA0 pad */
/* Set the sector size in the NFC to match the memory */
NFC_SECSZ = (PAGE_SIZE|(ECC_SIZE+1));
}
else /* (DATA_WIDTH == NFC_8BIT) */
{
NFC_CFG &= ~NFC_CFG_BITWIDTH_MASK;
PORTC_PCR5 = PORT_PCR_MUX(5) | PORT_PCR_DSE_MASK; /* Enable the NFC_DATA7 pad */
PORTC_PCR6 = PORT_PCR_MUX(5) | PORT_PCR_DSE_MASK; /* Enable the NFC_DATA6 pad */
PORTC_PCR7 = PORT_PCR_MUX(5) | PORT_PCR_DSE_MASK; /* Enable the NFC_DATA5 pad */
PORTC_PCR8 = PORT_PCR_MUX(5) | PORT_PCR_DSE_MASK; /* Enable the NFC_DATA4 pad */
PORTC_PCR9 = PORT_PCR_MUX(5) | PORT_PCR_DSE_MASK; /* Enable the NFC_DATA3 pad */
PORTC_PCR10 = PORT_PCR_MUX(5) | PORT_PCR_DSE_MASK; /* Enable the NFC_DATA2 pad */
PORTD_PCR4 = PORT_PCR_MUX(5) | PORT_PCR_DSE_MASK; /* Enable the NFC_DATA1 pad */
PORTD_PCR5 = PORT_PCR_MUX(5) | PORT_PCR_DSE_MASK; /* Enable the NFC_DATA0 pad */
/* Set the sector size in the NFC to match the memory */
NFC_SECSZ = (PAGE_SIZE | ECC_SIZE);
}
/* Configure NFC for EDO mode if defined in nand.h */
#if defined(NFC_EDO)
NFC_CFG |= NFC_CFG_FAST_MASK;
#endif
/* Disable auto address and buff num increment */
NFC_CFG &= ~(NFC_CFG_AIAD_MASK | NFC_CFG_AIBN_MASK);
/* Set NFC to STOP if a write error is detected */
NFC_CFG |= NFC_CFG_STOPWERR_MASK;
/* Disable row address increment */
NFC_RAI = 0;
/* Disable swap */
NFC_SWAP = 0;
}
void __pe_initialize_hardware(void)
{
_bsp_watchdog_disable();
#if MQX_ENABLE_LOW_POWER
/* Reset from LLWU wake up source */
if (_lpm_get_reset_source() == MQX_RESET_SOURCE_LLWU)
{
PMC_REGSC |= PMC_REGSC_ACKISO_MASK;
}
#endif
/*** !!! Here you can place your own code before PE initialization using property "User code before PE initialization" on the build options tab. !!! ***/
/*** ### MK70FN1M0VMJ12 "Cpu" init code ... ***/
/*** PE initialization code after reset ***/
/* SIM_SCGC6: RTC=1 */
SIM_SCGC6 |= (uint32_t)0x20000000UL;
if ((RTC_CR & RTC_CR_OSCE_MASK) == 0u) { /* Only if the OSCILLATOR is not already enabled */
/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
RTC_CR &= (uint32_t)~0x3C00UL;
/* RTC_CR: OSCE=1 */
RTC_CR |= (uint32_t)0x0100UL;
/* RTC_CR: CLKO=0 */
RTC_CR &= (uint32_t)~0x0200UL;
}
/* System clock initialization */
/* SIM_SCGC5: PORTE=1,PORTC=1,PORTA=1 */
SIM_SCGC5 |= (uint32_t)0x2A00UL; /* Enable clock gate for ports to enable pin routing */
if ( *((uint8_t*) 0x03FFU) != 0xFFU) {
MCG_C3 = *((uint8_t*) 0x03FFU);
MCG_C4 = (MCG_C4 & 0xE0U) | ((*((uint8_t*) 0x03FEU)) & 0x1FU);
}
/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=2,OUTDIV4=5,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM_CLKDIV1 = (uint32_t)0x01250000UL; /* Update system prescalers */
/* SIM_CLKDIV4: NFCDIV=7 */
SIM_CLKDIV4 |= SIM_CLKDIV4_NFCDIV(7);
/* SIM_SOPT2: PLLFLLSEL=1 */
SIM_SOPT2 = (uint32_t)((SIM_SOPT2 & (uint32_t)~0x00020000UL) | (uint32_t)0x00010000UL); /* Select PLL 0 as a clock source for various peripherals */
/* SIM_SOPT1: OSC32KSEL=1 */
SIM_SOPT1 |= (uint32_t)0x00080000UL; /* RTC oscillator drives 32 kHz clock for various peripherals */
/* SIM_SCGC1: OSC1=1 */
SIM_SCGC1 |= (uint32_t)0x20UL;
/* PORTA_PCR18: ISF=0,MUX=0 */
PORTA_PCR18 &= (uint32_t)~0x01000700UL;
/* PORTE_PCR24: ISF=0,MUX=0 */
PORTE_PCR24 &= (uint32_t)~0x01000700UL;
/* PORTE_PCR25: ISF=0,MUX=0 */
PORTE_PCR25 &= (uint32_t)~0x01000700UL;
/* Switch to FBE Mode */
/* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC0_CR = (uint8_t)0x80U;
/* OSC1_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC1_CR = (uint8_t)0x80U;
/* MCG_C7: OSCSEL=0 */
MCG_C7 &= (uint8_t)~(uint8_t)0x01U;
/* MCG_C10: LOCRE2=0,??=0,RANGE1=2,HGO1=1,EREFS1=1,??=0,??=0 */
MCG_C10 = (uint8_t)0x2CU;
/* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=1 */
MCG_C2 = (uint8_t)0x21U;
/* MCG_C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=0,IREFSTEN=0 */
MCG_C1 = (uint8_t)0xA8U;
/* MCG_C4: DMX32=0,DRST_DRS=0 */
MCG_C4 &= (uint8_t)~(uint8_t)0xE0U;
/* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=4 */
MCG_C5 = (uint8_t)0x04U;
/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=8 */
MCG_C6 = (uint8_t)0x08U;
/* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=3 */
MCG_C11 = (uint8_t)0x03U;
/* MCG_C11: PLLCLKEN1=1 */
MCG_C11 |= (uint8_t)0x40U; /* Enable the PLL */
/* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=8 */
MCG_C12 = (uint8_t)0x08U;
while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
}
while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
/* Switch to PBE Mode */
/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=8 */
MCG_C6 = (uint8_t)0x48U;
while((MCG_S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
}
while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL locked */
}
/* Switch to PEE Mode */
/* MCG_C1: CLKS=0,FRDIV=5,IREFS=0,IRCLKEN=0,IREFSTEN=0 */
MCG_C1 = (uint8_t)0x28U;
while((MCG_S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
}
/* MCG_C6: CME0=1 */
MCG_C6 |= (uint8_t)0x20U; /* Enable the clock monitor */
/*** End of PE initialization code after reset ***/
/*** !!! Here you can place your own code after PE initialization using property "User code after PE initialization" on the build options tab. !!! ***/
}
