C++ (Cpp) SIM_SOPT2_FBSL Examples

Example #1

File: init_hw.c Project: Vinhuit/Freescale

/*FUNCTION*---------------------------------------------------------------------
* 
* Function Name    : _bsp_flexbus_setup
* Returned Value   :  none
* Comments         :
*    Setup FlexBus pins for early MRAM operation
*
*END*-------------------------------------------------------------------------*/
static void _bsp_flexbus_setup (void) 
{
    #define ALT5                    0x05
    #define OFF_CHIP_ACCESS_ALLOW   3

    PORT_MemMapPtr  pctl;
    SIM_MemMapPtr   sim = SIM_BASE_PTR;
    FB_MemMapPtr    fb_ptr = FB_BASE_PTR;

    /* Enable clock to FlexBus module */
    sim->SCGC7 |= SIM_SCGC7_FLEXBUS_MASK;
    sim->SOPT2 |= SIM_SOPT2_FBSL(OFF_CHIP_ACCESS_ALLOW);

    pctl = (PORT_MemMapPtr)PORTB_BASE_PTR;
    pctl->PCR[10] = PORT_PCR_MUX(ALT5); /* FB_AD19 */
    pctl->PCR[11] = PORT_PCR_MUX(ALT5); /* FB_AD18 */
    pctl->PCR[16] = PORT_PCR_MUX(ALT5); /* FB_AD17 */
    pctl->PCR[17] = PORT_PCR_MUX(ALT5); /* FB_AD16 */
#if !BSPCFG_ENABLE_SAI
    pctl->PCR[18] = PORT_PCR_MUX(ALT5); /* FB_AD15 */
    pctl->PCR[19] = PORT_PCR_MUX(ALT5); /* FB_OE_b */
#endif
    pctl->PCR[20] = PORT_PCR_MUX(ALT5); /* FB_AD31 */
    pctl->PCR[21] = PORT_PCR_MUX(ALT5); /* FB_AD30 */
    pctl->PCR[22] = PORT_PCR_MUX(ALT5); /* FB_AD29 */
    pctl->PCR[23] = PORT_PCR_MUX(ALT5); /* FB_AD28 */
    
    pctl = (PORT_MemMapPtr)PORTC_BASE_PTR;
    pctl->PCR[0] = PORT_PCR_MUX(ALT5); /* FB_AD14 */
#if !BSPCFG_ENABLE_SAI
    pctl->PCR[1] = PORT_PCR_MUX(ALT5); /* FB_AD13 */
    pctl->PCR[5] = PORT_PCR_MUX(ALT5); /* FB_AD10 */
    pctl->PCR[6] = PORT_PCR_MUX(ALT5); /* FB_AD9 */
#endif
    pctl->PCR[2] = PORT_PCR_MUX(ALT5); /* FB_AD12 */
    pctl->PCR[3] = PORT_PCR_MUX(ALT5); /* FB_CLKOUT */
    pctl->PCR[4] = PORT_PCR_MUX(ALT5); /* FB_AD11 */
    pctl->PCR[7] = PORT_PCR_MUX(ALT5); /* FB_AD8 */
    pctl->PCR[8] = PORT_PCR_MUX(ALT5); /* FB_AD7 */
    pctl->PCR[9] = PORT_PCR_MUX(ALT5); /* FB_AD6 */
    pctl->PCR[10] = PORT_PCR_MUX(ALT5); /* FB_AD5 */
    pctl->PCR[11] = PORT_PCR_MUX(ALT5); /* FB_RW_b */
    pctl->PCR[12] = PORT_PCR_MUX(ALT5); /* FB_AD27 */
    pctl->PCR[13] = PORT_PCR_MUX(ALT5); /* FB_AD26 */
    pctl->PCR[14] = PORT_PCR_MUX(ALT5); /* FB_AD25 */
    pctl->PCR[15] = PORT_PCR_MUX(ALT5); /* FB_AD24 */
    
    pctl = (PORT_MemMapPtr)PORTD_BASE_PTR;
    pctl->PCR[0] = PORT_PCR_MUX(ALT5); /* FB_ALE */
    pctl->PCR[1] = PORT_PCR_MUX(ALT5); /* FB_CS0_b */
    pctl->PCR[2] = PORT_PCR_MUX(ALT5); /* FB_AD4 */
    pctl->PCR[3] = PORT_PCR_MUX(ALT5); /* FB_AD3 */
    pctl->PCR[4] = PORT_PCR_MUX(ALT5); /* FB_AD2 */
    pctl->PCR[5] = PORT_PCR_MUX(ALT5); /* FB_AD1 */
    pctl->PCR[6] = PORT_PCR_MUX(ALT5); /* FB_AD0 */

    /* configure chip select multiplexers (CS1) */
    fb_ptr->CSPMCR=FB_CSPMCR_GROUP1(1);
}

Example #2

File: init_hw.c Project: gaodebang/eth-com-project

/*FUNCTION*---------------------------------------------------------------------
* 
* Function Name    : _bsp_flexbus_setup
* Returned Value   :  none
* Comments         :
*    Setup FlexBus pins for early MRAM operation
*
*END*-------------------------------------------------------------------------*/
static void _bsp_flexbus_setup (void) 
{
    #define ALT5                    0x05
    #define OFF_CHIP_ACCESS_ALLOW   3

    PORT_MemMapPtr  pctl;
    SIM_MemMapPtr   sim = SIM_BASE_PTR;

    /* Enable clock to FlexBus module */
    sim->SCGC7 |= SIM_SCGC7_FLEXBUS_MASK;
    sim->SOPT2 |= SIM_SOPT2_FBSL(OFF_CHIP_ACCESS_ALLOW);

    pctl = (PORT_MemMapPtr)PORTE_BASE_PTR;
    pctl->PCR[6] = PORT_PCR_MUX(ALT5); /* FB_ALE */
    pctl->PCR[7] = PORT_PCR_MUX(ALT5); /* FB_CS0_b */
    pctl->PCR[8] = PORT_PCR_MUX(ALT5); /* FB_AD4 */
    pctl->PCR[9] = PORT_PCR_MUX(ALT5); /* FB_AD3 */
    pctl->PCR[10] = PORT_PCR_MUX(ALT5); /* FB_AD2 */
    pctl->PCR[11] = PORT_PCR_MUX(ALT5); /* FB_AD1 */
    pctl->PCR[12] = PORT_PCR_MUX(ALT5); /* FB_AD0 */

    pctl = (PORT_MemMapPtr)PORTA_BASE_PTR;
    pctl->PCR[6] = PORT_PCR_MUX(ALT5); /* FB_CLKOUT */
    pctl->PCR[7] = PORT_PCR_MUX(ALT5); /* FB_AD18 */
    pctl->PCR[8] = PORT_PCR_MUX(ALT5); /* FB_AD17 */
    pctl->PCR[9] = PORT_PCR_MUX(ALT5); /* FB_AD16 */
    pctl->PCR[10] = PORT_PCR_MUX(ALT5); /* FB_AD15 */
    pctl->PCR[11] = PORT_PCR_MUX(ALT5); /* FB_OE_b */
    pctl->PCR[24] = PORT_PCR_MUX(ALT5); /* FB_AD14 */
    pctl->PCR[25] = PORT_PCR_MUX(ALT5); /* FB_AD13 */
    pctl->PCR[26] = PORT_PCR_MUX(ALT5); /* FB_AD12 */
    pctl->PCR[27] = PORT_PCR_MUX(ALT5); /* FB_AD11 */
    pctl->PCR[28] = PORT_PCR_MUX(ALT5); /* FB_AD10 */
    pctl->PCR[29] = PORT_PCR_MUX(ALT5); /* FB_AD19 */

    pctl = (PORT_MemMapPtr)PORTD_BASE_PTR;
    pctl->PCR[10] = PORT_PCR_MUX(ALT5); /* FB_AD9 */
    pctl->PCR[11] = PORT_PCR_MUX(ALT5); /* FB_AD8 */
    pctl->PCR[12] = PORT_PCR_MUX(ALT5); /* FB_AD7 */
    pctl->PCR[13] = PORT_PCR_MUX(ALT5); /* FB_AD6 */
    pctl->PCR[14] = PORT_PCR_MUX(ALT5); /* FB_AD5 */
    pctl->PCR[15] = PORT_PCR_MUX(ALT5); /* FB_RW_b */
}